Joerg Wunsch wrote:
As Joel Sherrill wrote:
FYI the avr .h file has this:
io4433.h:/* 0x3D..0x3E SP */
Is this by convention?
Yes, that's GCC's frame pointer management. We know this is slightly
incorrect, but GCC classifies AVRs into a few rather coarse CPU models
for its code generation, and the actual size of the accessible SRAM
(and thus the stack pointer width) is not part of that classification,
so the SPH register is always manipulated. So far, none of the
(non-Xmega) AVRs has broken the model of using fixed addresses for
SPL, SPH, and SREG. Those devices that only feature SRAM addresses
below 0x100 (and thus don't need SPH) have IO location 0x3E as a
reserved IO register where writing to it does not harm, and reading
from it yields anything which actually nobody cares about (except of
writing it back later on).
Just to make sure I am understanding correctly. :)
0x3d - 0x3e should allow writes but a read does not
have to return the value previously written?
Or is it acceptable to mirror back the value written.
Then it can use RWMemoryWithOwnMemory() which
already exists.
And this should be the behaviour on all current models
supported:
at90s4433
at90s8515
atmega48
atmega128
Thinking outload, it might be nice to have a "RWNotImplemented"
class so it can know the name of the location and give a nice
plea to pitch in. :)
So in light of this technique, simulavrxx should probably by default
ignore access attempts to SPH even on CPUs that don't have it. (I
know VMlab always complains about it, it can be a little annoying.)
I don't like warnings or hints of errors. I have spent too
much of my career hunting ghosts. If something prints
a message, I want it to be meaningful.
Thanks.
--
Joel Sherrill, Ph.D. Director of Research & Development
[email protected] On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
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