Module Name: src
Committed By: simonb
Date: Fri Jun 19 02:23:43 UTC 2020
Modified Files:
src/sys/arch/mips/cavium: octeon_intr.c
src/sys/arch/mips/cavium/dev: octeon_ciureg.h octeon_dwctwo.c
octeon_gmx.c octeon_ipd.c octeon_mpi.c octeon_pci.c octeon_pow.c
octeon_uart.c
Log Message:
Simplify interrupt definition: remove mostly unused masks and just
configure everything using interrupt numbers.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/cavium/octeon_intr.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/cavium/dev/octeon_ciureg.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/cavium/dev/octeon_dwctwo.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/cavium/dev/octeon_gmx.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/cavium/dev/octeon_ipd.c \
src/sys/arch/mips/cavium/dev/octeon_mpi.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/cavium/dev/octeon_pci.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/cavium/dev/octeon_pow.c \
src/sys/arch/mips/cavium/dev/octeon_uart.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/octeon_intr.c
diff -u src/sys/arch/mips/cavium/octeon_intr.c:1.11 src/sys/arch/mips/cavium/octeon_intr.c:1.12
--- src/sys/arch/mips/cavium/octeon_intr.c:1.11 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/octeon_intr.c Fri Jun 19 02:23:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_intr.c,v 1.11 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_intr.c,v 1.12 2020/06/19 02:23:43 simonb Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
@@ -45,7 +45,7 @@
#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.11 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.12 2020/06/19 02:23:43 simonb Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -163,13 +163,13 @@ struct octeon_intrhand ipi_intrhands[2]
[0] = {
.ih_func = octeon_ipi_intr,
.ih_arg = (void *)(uintptr_t)__BITS(15,0),
- .ih_irq = _CIU_INT_MBOX_15_0_SHIFT,
+ .ih_irq = CIU_INT_MBOX_15_0,
.ih_ipl = IPL_SCHED,
},
[1] = {
.ih_func = octeon_ipi_intr,
.ih_arg = (void *)(uintptr_t)__BITS(31,16),
- .ih_irq = _CIU_INT_MBOX_31_16_SHIFT,
+ .ih_irq = CIU_INT_MBOX_31_16,
.ih_ipl = IPL_HIGH,
},
};
@@ -177,8 +177,8 @@ struct octeon_intrhand ipi_intrhands[2]
struct octeon_intrhand *octciu_intrs[NIRQS] = {
#ifdef MULTIPROCESSOR
- [_CIU_INT_MBOX_15_0_SHIFT] = &ipi_intrhands[0],
- [_CIU_INT_MBOX_31_16_SHIFT] = &ipi_intrhands[1],
+ [CIU_INT_MBOX_15_0] = &ipi_intrhands[0],
+ [CIU_INT_MBOX_31_16] = &ipi_intrhands[1],
#endif
};
@@ -212,6 +212,7 @@ struct cpu_softc octeon_cpu0_softc = {
};
#ifdef MULTIPROCESSOR
+/* XXX limit of two CPUs ... */
struct cpu_softc octeon_cpu1_softc = {
.cpu_int0_sum0 = X(CIU_INT2_SUM0),
.cpu_int1_sum0 = X(CIU_INT3_SUM0),
@@ -227,7 +228,7 @@ struct cpu_softc octeon_cpu1_softc = {
.cpu_int32_en = X(CIU_INT32_EN1),
- .cpu_wdog = X(CIU_WDOG1),
+ .cpu_wdog = X(CIU_WDOG(1)),
.cpu_pp_poke = X(CIU_PP_POKE1),
.cpu_mbox_set = X(CIU_MBOX_SET1),
@@ -245,8 +246,8 @@ octeon_mbox_test(void)
const uint64_t mbox_set1 = X(CIU_MBOX_SET1);
const uint64_t int_sum0 = X(CIU_INT0_SUM0);
const uint64_t int_sum1 = X(CIU_INT2_SUM0);
- const uint64_t sum_mbox_lo = __BIT(_CIU_INT_MBOX_15_0_SHIFT);
- const uint64_t sum_mbox_hi = __BIT(_CIU_INT_MBOX_31_16_SHIFT);
+ const uint64_t sum_mbox_lo = __BIT(CIU_INT_MBOX_15_0);
+ const uint64_t sum_mbox_hi = __BIT(CIU_INT_MBOX_31_16);
mips3_sd(mbox_clr0, ~0ULL);
mips3_sd(mbox_clr1, ~0ULL);
@@ -328,8 +329,8 @@ octeon_intr_init(struct cpu_info *ci)
#ifdef MULTIPROCESSOR
// Enable the IPIs
- cpu->cpu_int1_enable0 |= __BIT(_CIU_INT_MBOX_15_0_SHIFT);
- cpu->cpu_int2_enable0 |= __BIT(_CIU_INT_MBOX_31_16_SHIFT);
+ cpu->cpu_int1_enable0 |= __BIT(CIU_INT_MBOX_15_0);
+ cpu->cpu_int2_enable0 |= __BIT(CIU_INT_MBOX_31_16);
#endif
if (ci->ci_dev)
Index: src/sys/arch/mips/cavium/dev/octeon_ciureg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_ciureg.h:1.6 src/sys/arch/mips/cavium/dev/octeon_ciureg.h:1.7
--- src/sys/arch/mips/cavium/dev/octeon_ciureg.h:1.6 Tue Jun 2 14:39:57 2020
+++ src/sys/arch/mips/cavium/dev/octeon_ciureg.h Fri Jun 19 02:23:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ciureg.h,v 1.6 2020/06/02 14:39:57 simonb Exp $ */
+/* $NetBSD: octeon_ciureg.h,v 1.7 2020/06/19 02:23:43 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -56,7 +56,7 @@
#define CIU_TIM2 UINT64_C(0x0001070000000490)
#define CIU_TIM3 UINT64_C(0x0001070000000498)
#define CIU_WDOG0 UINT64_C(0x0001070000000500)
-#define CIU_WDOG1 UINT64_C(0x0001070000000508)
+#define CIU_WDOG(n) (CIU_WDOG0 + (n) * 8)
#define CIU_PP_POKE0 UINT64_C(0x0001070000000580)
#define CIU_PP_POKE1 UINT64_C(0x0001070000000588)
#define CIU_MBOX_SET0 UINT64_C(0x0001070000000600)
@@ -125,213 +125,89 @@
/* ---- register bits */
-/* ``interrupt bits'' shift values */
+/* interrupt numbers */
-#define _CIU_INT_XXX_63_SHIFT 0x3f
-#define _CIU_INT_XXX_62_SHIFT 0x3e
-#define _CIU_INT_XXX_61_SHIFT 0x3d
-#define _CIU_INT_XXX_60_SHIFT 0x3c
-#define _CIU_INT_XXX_59_SHIFT 0x3b
-#define _CIU_INT_MPI_SHIFT 0x3a
-#define _CIU_INT_PCM_SHIFT 0x39
-#define _CIU_INT_USB_SHIFT 0x38
-#define _CIU_INT_TIMER_3_SHIFT 0x37
-#define _CIU_INT_TIMER_2_SHIFT 0x36
-#define _CIU_INT_TIMER_1_SHIFT 0x35
-#define _CIU_INT_TIMER_0_SHIFT 0x34
-#define _CIU_INT_XXX_51_SHIFT 0x33
-#define _CIU_INT_IPD_DRP_SHIFT 0x32
-#define _CIU_INT_GMX_DRP_SHIFT 0x30
-#define _CIU_INT_TRACE_SHIFT 0x2f
-#define _CIU_INT_RML_SHIFT 0x2e
-#define _CIU_INT_TWSI_SHIFT 0x2d
-#define _CIU_INT_WDOG_SUM_SHIFT 0x2c
-#define _CIU_INT_PCI_MSI_63_48_SHIFT 0x2b
-#define _CIU_INT_PCI_MSI_47_32_SHIFT 0x2a
-#define _CIU_INT_PCI_MSI_31_16_SHIFT 0x29
-#define _CIU_INT_PCI_MSI_15_0_SHIFT 0x28
-#define _CIU_INT_PCI_INT_D_SHIFT 0x27
-#define _CIU_INT_PCI_INT_C_SHIFT 0x26
-#define _CIU_INT_PCI_INT_B_SHIFT 0x25
-#define _CIU_INT_PCI_INT_A_SHIFT 0x24
-#define _CIU_INT_UART_1_SHIFT 0x23
-#define _CIU_INT_UART_0_SHIFT 0x22
-#define _CIU_INT_MBOX_31_16_SHIFT 0x21
-#define _CIU_INT_MBOX_15_0_SHIFT 0x20
-#define _CIU_INT_GPIO_15_SHIFT 0x1f
-#define _CIU_INT_GPIO_14_SHIFT 0x1e
-#define _CIU_INT_GPIO_13_SHIFT 0x1d
-#define _CIU_INT_GPIO_12_SHIFT 0x1c
-#define _CIU_INT_GPIO_11_SHIFT 0x1b
-#define _CIU_INT_GPIO_10_SHIFT 0x1a
-#define _CIU_INT_GPIO_9_SHIFT 0x19
-#define _CIU_INT_GPIO_8_SHIFT 0x18
-#define _CIU_INT_GPIO_7_SHIFT 0x17
-#define _CIU_INT_GPIO_6_SHIFT 0x16
-#define _CIU_INT_GPIO_5_SHIFT 0x15
-#define _CIU_INT_GPIO_4_SHIFT 0x14
-#define _CIU_INT_GPIO_3_SHIFT 0x13
-#define _CIU_INT_GPIO_2_SHIFT 0x12
-#define _CIU_INT_GPIO_1_SHIFT 0x11
-#define _CIU_INT_GPIO_0_SHIFT 0x10
-#define _CIU_INT_WORKQ_15_SHIFT 0x0f
-#define _CIU_INT_WORKQ_14_SHIFT 0x0e
-#define _CIU_INT_WORKQ_13_SHIFT 0x0d
-#define _CIU_INT_WORKQ_12_SHIFT 0x0c
-#define _CIU_INT_WORKQ_11_SHIFT 0x0b
-#define _CIU_INT_WORKQ_10_SHIFT 0x0a
-#define _CIU_INT_WORKQ_9_SHIFT 0x09
-#define _CIU_INT_WORKQ_8_SHIFT 0x08
-#define _CIU_INT_WORKQ_7_SHIFT 0x07
-#define _CIU_INT_WORKQ_6_SHIFT 0x06
-#define _CIU_INT_WORKQ_5_SHIFT 0x05
-#define _CIU_INT_WORKQ_4_SHIFT 0x04
-#define _CIU_INT_WORKQ_3_SHIFT 0x03
-#define _CIU_INT_WORKQ_2_SHIFT 0x02
-#define _CIU_INT_WORKQ_1_SHIFT 0x01
-#define _CIU_INT_WORKQ_0_SHIFT 0x00
-
-#define CIU_INTX_SUM0_XXX_63_59 UINT64_C(0xf800000000000000)
-#define CIU_INTX_SUM0_MPI UINT64_C(0x0400000000000000)
-#define CIU_INTX_SUM0_PCM UINT64_C(0x0200000000000000)
-#define CIU_INTX_SUM0_USB UINT64_C(0x0100000000000000)
-#define CIU_INTX_SUM0_TIMER UINT64_C(0x00f0000000000000)
-#define CIU_INTX_SUM0_TIMER_3 UINT64_C(0x0080000000000000)
-#define CIU_INTX_SUM0_TIMER_2 UINT64_C(0x0040000000000000)
-#define CIU_INTX_SUM0_TIMER_1 UINT64_C(0x0020000000000000)
-#define CIU_INTX_SUM0_TIMER_0 UINT64_C(0x0010000000000000)
-#define CIU_INTX_SUM0_XXX_51 UINT64_C(0x0008000000000000)
-#define CIU_INTX_SUM0_IPD_DRP UINT64_C(0x0004000000000000)
-#define CIU_INTX_SUM0_XXX_49 UINT64_C(0x0002000000000000)
-#define CIU_INTX_SUM0_GMX_DRP UINT64_C(0x0001000000000000)
-#define CIU_INTX_SUM0_TRACE UINT64_C(0x0000800000000000)
-#define CIU_INTX_SUM0_RML UINT64_C(0x0000400000000000)
-#define CIU_INTX_SUM0_TWSI UINT64_C(0x0000200000000000)
-#define CIU_INTX_SUM0_WDOG_SUM UINT64_C(0x0000100000000000)
-#define CIU_INTX_SUM0_PCI_MSI UINT64_C(0x00000f0000000000)
-#define CIU_INTX_SUM0_PCI_MSI_63_48 UINT64_C(0x0000080000000000)
-#define CIU_INTX_SUM0_PCI_MSI_47_32 UINT64_C(0x0000040000000000)
-#define CIU_INTX_SUM0_PCI_MSI_31_16 UINT64_C(0x0000020000000000)
-#define CIU_INTX_SUM0_PCI_MSI_15_0 UINT64_C(0x0000010000000000)
-#define CIU_INTX_SUM0_PCI_INT UINT64_C(0x000000f000000000)
-#define CIU_INTX_SUM0_PCI_INT_D UINT64_C(0x0000008000000000)
-#define CIU_INTX_SUM0_PCI_INT_C UINT64_C(0x0000004000000000)
-#define CIU_INTX_SUM0_PCI_INT_B UINT64_C(0x0000002000000000)
-#define CIU_INTX_SUM0_PCI_INT_A UINT64_C(0x0000001000000000)
-#define CIU_INTX_SUM0_UART UINT64_C(0x0000000c00000000)
-#define CIU_INTX_SUM0_UART_1 UINT64_C(0x0000000800000000)
-#define CIU_INTX_SUM0_UART_0 UINT64_C(0x0000000400000000)
-#define CIU_INTX_SUM0_MBOX UINT64_C(0x0000000300000000)
-#define CIU_INTX_SUM0_MBOX_31_16 UINT64_C(0x0000000200000000)
-#define CIU_INTX_SUM0_MBOX_15_0 UINT64_C(0x0000000100000000)
-#define CIU_INTX_SUM0_GPIO UINT64_C(0x00000000ffff0000)
-#define CIU_INTX_SUM0_GPIO_15 UINT64_C(0x0000000080000000)
-#define CIU_INTX_SUM0_GPIO_14 UINT64_C(0x0000000040000000)
-#define CIU_INTX_SUM0_GPIO_13 UINT64_C(0x0000000020000000)
-#define CIU_INTX_SUM0_GPIO_12 UINT64_C(0x0000000010000000)
-#define CIU_INTX_SUM0_GPIO_11 UINT64_C(0x0000000008000000)
-#define CIU_INTX_SUM0_GPIO_10 UINT64_C(0x0000000004000000)
-#define CIU_INTX_SUM0_GPIO_9 UINT64_C(0x0000000002000000)
-#define CIU_INTX_SUM0_GPIO_8 UINT64_C(0x0000000001000000)
-#define CIU_INTX_SUM0_GPIO_7 UINT64_C(0x0000000000800000)
-#define CIU_INTX_SUM0_GPIO_6 UINT64_C(0x0000000000400000)
-#define CIU_INTX_SUM0_GPIO_5 UINT64_C(0x0000000000200000)
-#define CIU_INTX_SUM0_GPIO_4 UINT64_C(0x0000000000100000)
-#define CIU_INTX_SUM0_GPIO_3 UINT64_C(0x0000000000080000)
-#define CIU_INTX_SUM0_GPIO_2 UINT64_C(0x0000000000040000)
-#define CIU_INTX_SUM0_GPIO_1 UINT64_C(0x0000000000020000)
-#define CIU_INTX_SUM0_GPIO_0 UINT64_C(0x0000000000010000)
-#define CIU_INTX_SUM0_WORKQ UINT64_C(0x000000000000ffff)
-#define CIU_INTX_SUM0_WORKQ_15 UINT64_C(0x0000000000008000)
-#define CIU_INTX_SUM0_WORKQ_14 UINT64_C(0x0000000000004000)
-#define CIU_INTX_SUM0_WORKQ_13 UINT64_C(0x0000000000002000)
-#define CIU_INTX_SUM0_WORKQ_12 UINT64_C(0x0000000000001000)
-#define CIU_INTX_SUM0_WORKQ_11 UINT64_C(0x0000000000000800)
-#define CIU_INTX_SUM0_WORKQ_10 UINT64_C(0x0000000000000400)
-#define CIU_INTX_SUM0_WORKQ_9 UINT64_C(0x0000000000000200)
-#define CIU_INTX_SUM0_WORKQ_8 UINT64_C(0x0000000000000100)
-#define CIU_INTX_SUM0_WORKQ_7 UINT64_C(0x0000000000000080)
-#define CIU_INTX_SUM0_WORKQ_6 UINT64_C(0x0000000000000040)
-#define CIU_INTX_SUM0_WORKQ_5 UINT64_C(0x0000000000000020)
-#define CIU_INTX_SUM0_WORKQ_4 UINT64_C(0x0000000000000010)
-#define CIU_INTX_SUM0_WORKQ_3 UINT64_C(0x0000000000000008)
-#define CIU_INTX_SUM0_WORKQ_2 UINT64_C(0x0000000000000004)
-#define CIU_INTX_SUM0_WORKQ_1 UINT64_C(0x0000000000000002)
-#define CIU_INTX_SUM0_WORKQ_0 UINT64_C(0x0000000000000001)
-
-#define CIU_INT_SUM1_XXX_63_1 UINT64_C(0xfffffffffffffffe)
-#define CIU_INT_SUM1_WDOG UINT64_C(0x0000000000000001)
-
-#define CIU_INTX_EN0_XXX_63_59 UINT64_C(0xf800000000000000)
-#define CIU_INTX_EN0_MPI UINT64_C(0x0400000000000000)
-#define CIU_INTX_EN0_PCM UINT64_C(0x0200000000000000)
-#define CIU_INTX_EN0_USB UINT64_C(0x0100000000000000)
-#define CIU_INTX_EN0_TIMER UINT64_C(0x00f0000000000000)
-#define CIU_INTX_EN0_TIMER_3 UINT64_C(0x0080000000000000)
-#define CIU_INTX_EN0_TIMER_2 UINT64_C(0x0040000000000000)
-#define CIU_INTX_EN0_TIMER_1 UINT64_C(0x0020000000000000)
-#define CIU_INTX_EN0_TIMER_0 UINT64_C(0x0010000000000000)
-#define CIU_INTX_EN0_XXX_51 UINT64_C(0x0008000000000000)
-#define CIU_INTX_EN0_IPD_DRP UINT64_C(0x0004000000000000)
-#define CIU_INTX_EN0_XXX_49 UINT64_C(0x0002000000000000)
-#define CIU_INTX_EN0_GMX_DRP UINT64_C(0x0001000000000000)
-#define CIU_INTX_EN0_TRACE UINT64_C(0x0000800000000000)
-#define CIU_INTX_EN0_RML UINT64_C(0x0000400000000000)
-#define CIU_INTX_EN0_TWSI UINT64_C(0x0000200000000000)
-#define CIU_INTX_EN0_WDOG_SUM UINT64_C(0x0000100000000000)
-#define CIU_INTX_EN0_PCI_MSI UINT64_C(0x00000f0000000000)
-#define CIU_INTX_EN0_PCI_MSI_63_48 UINT64_C(0x0000080000000000)
-#define CIU_INTX_EN0_PCI_MSI_47_32 UINT64_C(0x0000040000000000)
-#define CIU_INTX_EN0_PCI_MSI_31_16 UINT64_C(0x0000020000000000)
-#define CIU_INTX_EN0_PCI_MSI_15_0 UINT64_C(0x0000010000000000)
-#define CIU_INTX_EN0_PCI_INT UINT64_C(0x000000f000000000)
-#define CIU_INTX_EN0_PCI_INT_D UINT64_C(0x0000008000000000)
-#define CIU_INTX_EN0_PCI_INT_C UINT64_C(0x0000004000000000)
-#define CIU_INTX_EN0_PCI_INT_B UINT64_C(0x0000002000000000)
-#define CIU_INTX_EN0_PCI_INT_A UINT64_C(0x0000001000000000)
-#define CIU_INTX_EN0_UART UINT64_C(0x0000000c00000000)
-#define CIU_INTX_EN0_UART_1 UINT64_C(0x0000000800000000)
-#define CIU_INTX_EN0_UART_0 UINT64_C(0x0000000400000000)
-#define CIU_INTX_EN0_MBOX UINT64_C(0x0000000300000000)
-#define CIU_INTX_EN0_MBOX_31_16 UINT64_C(0x0000000200000000)
-#define CIU_INTX_EN0_MBOX_15_0 UINT64_C(0x0000000100000000)
-#define CIU_INTX_EN0_GPIO UINT64_C(0x00000000ffff0000)
-#define CIU_INTX_EN0_GPIO_15 UINT64_C(0x0000000080000000)
-#define CIU_INTX_EN0_GPIO_14 UINT64_C(0x0000000040000000)
-#define CIU_INTX_EN0_GPIO_13 UINT64_C(0x0000000020000000)
-#define CIU_INTX_EN0_GPIO_12 UINT64_C(0x0000000010000000)
-#define CIU_INTX_EN0_GPIO_11 UINT64_C(0x0000000008000000)
-#define CIU_INTX_EN0_GPIO_10 UINT64_C(0x0000000004000000)
-#define CIU_INTX_EN0_GPIO_9 UINT64_C(0x0000000002000000)
-#define CIU_INTX_EN0_GPIO_8 UINT64_C(0x0000000001000000)
-#define CIU_INTX_EN0_GPIO_7 UINT64_C(0x0000000000800000)
-#define CIU_INTX_EN0_GPIO_6 UINT64_C(0x0000000000400000)
-#define CIU_INTX_EN0_GPIO_5 UINT64_C(0x0000000000200000)
-#define CIU_INTX_EN0_GPIO_4 UINT64_C(0x0000000000100000)
-#define CIU_INTX_EN0_GPIO_3 UINT64_C(0x0000000000080000)
-#define CIU_INTX_EN0_GPIO_2 UINT64_C(0x0000000000040000)
-#define CIU_INTX_EN0_GPIO_1 UINT64_C(0x0000000000020000)
-#define CIU_INTX_EN0_GPIO_0 UINT64_C(0x0000000000010000)
-#define CIU_INTX_EN0_WORKQ UINT64_C(0x000000000000ffff)
-#define CIU_INTX_EN0_WORKQ_15 UINT64_C(0x0000000000008000)
-#define CIU_INTX_EN0_WORKQ_14 UINT64_C(0x0000000000004000)
-#define CIU_INTX_EN0_WORKQ_13 UINT64_C(0x0000000000002000)
-#define CIU_INTX_EN0_WORKQ_12 UINT64_C(0x0000000000001000)
-#define CIU_INTX_EN0_WORKQ_11 UINT64_C(0x0000000000000800)
-#define CIU_INTX_EN0_WORKQ_10 UINT64_C(0x0000000000000400)
-#define CIU_INTX_EN0_WORKQ_9 UINT64_C(0x0000000000000200)
-#define CIU_INTX_EN0_WORKQ_8 UINT64_C(0x0000000000000100)
-#define CIU_INTX_EN0_WORKQ_7 UINT64_C(0x0000000000000080)
-#define CIU_INTX_EN0_WORKQ_6 UINT64_C(0x0000000000000040)
-#define CIU_INTX_EN0_WORKQ_5 UINT64_C(0x0000000000000020)
-#define CIU_INTX_EN0_WORKQ_4 UINT64_C(0x0000000000000010)
-#define CIU_INTX_EN0_WORKQ_3 UINT64_C(0x0000000000000008)
-#define CIU_INTX_EN0_WORKQ_2 UINT64_C(0x0000000000000004)
-#define CIU_INTX_EN0_WORKQ_1 UINT64_C(0x0000000000000002)
-#define CIU_INTX_EN0_WORKQ_0 UINT64_C(0x0000000000000001)
-
-#define CIU_INTX_EN1_XXX_63_1 UINT64_C(0xfffffffffffffffe)
-#define CIU_INTX_EN1_WDOG UINT64_C(0x0000000000000001)
+#define CIU_INT_BOOTDMA 63
+#define CIU_INT_MII 62
+#define CIU_INT_IPDPPTHR 61
+#define CIU_INT_POWIQ 60
+#define CIU_INT_TWSI2 59
+#define CIU_INT_MPI 58
+#define CIU_INT_PCM 57
+#define CIU_INT_USB 56
+#define CIU_INT_TIMER_3 55
+#define CIU_INT_TIMER_2 54
+#define CIU_INT_TIMER_1 53
+#define CIU_INT_TIMER_0 52
+#define CIU_INT_KEY_ZERO 51
+#define CIU_INT_IPD_DRP 50
+#define CIU_INT_GMX_DRP2 49
+#define CIU_INT_GMX_DRP 48
+#define CIU_INT_TRACE 47
+#define CIU_INT_RML 46
+#define CIU_INT_TWSI 45
+#define CIU_INT_WDOG_SUM 44
+#define CIU_INT_PCI_MSI_63_48 43
+#define CIU_INT_PCI_MSI_47_32 42
+#define CIU_INT_PCI_MSI_31_16 41
+#define CIU_INT_PCI_MSI_15_0 40
+#define CIU_INT_PCI_INT_D 39
+#define CIU_INT_PCI_INT_C 38
+#define CIU_INT_PCI_INT_B 37
+#define CIU_INT_PCI_INT_A 36
+#define CIU_INT_UART_1 35
+#define CIU_INT_UART_0 34
+#define CIU_INT_MBOX_31_16 33
+#define CIU_INT_MBOX_15_0 32
+#define CIU_INT_GPIO_15 31
+#define CIU_INT_GPIO_14 30
+#define CIU_INT_GPIO_13 29
+#define CIU_INT_GPIO_12 28
+#define CIU_INT_GPIO_11 27
+#define CIU_INT_GPIO_10 26
+#define CIU_INT_GPIO_9 25
+#define CIU_INT_GPIO_8 24
+#define CIU_INT_GPIO_7 23
+#define CIU_INT_GPIO_6 22
+#define CIU_INT_GPIO_5 21
+#define CIU_INT_GPIO_4 20
+#define CIU_INT_GPIO_3 19
+#define CIU_INT_GPIO_2 18
+#define CIU_INT_GPIO_1 17
+#define CIU_INT_GPIO_0 16
+#define CIU_INT_WORKQ_15 15
+#define CIU_INT_WORKQ_14 14
+#define CIU_INT_WORKQ_13 13
+#define CIU_INT_WORKQ_12 12
+#define CIU_INT_WORKQ_11 11
+#define CIU_INT_WORKQ_10 10
+#define CIU_INT_WORKQ_9 9
+#define CIU_INT_WORKQ_8 8
+#define CIU_INT_WORKQ_7 7
+#define CIU_INT_WORKQ_6 6
+#define CIU_INT_WORKQ_5 5
+#define CIU_INT_WORKQ_4 4
+#define CIU_INT_WORKQ_3 3
+#define CIU_INT_WORKQ_2 2
+#define CIU_INT_WORKQ_1 1
+#define CIU_INT_WORKQ_0 0
+
+#define CUI_INT_WDOG_15 15
+#define CUI_INT_WDOG_14 14
+#define CUI_INT_WDOG_13 13
+#define CUI_INT_WDOG_12 12
+#define CUI_INT_WDOG_11 11
+#define CUI_INT_WDOG_10 10
+#define CUI_INT_WDOG_9 9
+#define CUI_INT_WDOG_8 8
+#define CUI_INT_WDOG_7 7
+#define CUI_INT_WDOG_6 6
+#define CUI_INT_WDOG_5 5
+#define CUI_INT_WDOG_4 4
+#define CUI_INT_WDOG_3 3
+#define CUI_INT_WDOG_2 2
+#define CUI_INT_WDOG_1 1
+#define CUI_INT_WDOG_0 0
#define CIU_TIMX_XXX_63_37 UINT64_C(0xffffffe000000000)
#define CIU_TIMX_ONE_SHOT UINT64_C(0x0000001000000000)
@@ -344,6 +220,10 @@
#define CIU_WDOGX_LEN UINT64_C(0x00000000000ffff0)
#define CIU_WDOGX_STATE UINT64_C(0x000000000000000c)
#define CIU_WDOGX_MODE UINT64_C(0x0000000000000003)
+#define CIU_WDOGX_MODE_OFF 0
+#define CIU_WDOGX_MODE_INTR 1
+#define CIU_WDOGX_MODE_INTR_NMI 2
+#define CIU_WDOGX_MODE_INTR_NMI_SOFT 3
#define CIU_PP_POKEX_XXX_63_0 UINT64_C(0xffffffffffffffff)
@@ -353,27 +233,21 @@
#define CIU_MBOX_CLRX_XXX_63_32 UINT64_C(0xffffffff00000000)
#define CIU_MBOX_CLRX_CLR UINT64_C(0x00000000ffffffff)
-#define CIU_PP_RST_XXX_63_2 UINT64_C(0xfffffffffffffffc)
-#define CIU_PP_RST_RST UINT64_C(0x0000000000000002)
+#define CIU_PP_RST_RST UINT64_C(0x0000ffffffffffff)
#define CIU_PP_RST_RST0 UINT64_C(0x0000000000000001)
-#define CIU_PP_DBG_XXX_63_1 UINT64_C(0xfffffffffffffffe)
-#define CIU_PP_DBG_PPDBG UINT64_C(0x0000000000000001)
+#define CIU_PP_DBG_PPDBG UINT64_C(0x0000ffffffffffff)
#define CIU_GSTOP_XXX_63_1 UINT64_C(0xfffffffffffffffe)
#define CIU_GSTOP_GSTOP UINT64_C(0x0000000000000001)
-#define CIU_NMI_XXX_63_2 UINT64_C(0xfffffffffffffffc)
-#define CIU_NMI_NMI UINT64_C(0x0000000000000003)
+#define CIU_NMI_NMI UINT64_C(0x0000ffffffffffff)
-#define CIU_DINT_XXX_63_2 UINT64_C(0xfffffffffffffffc)
-#define CIU_DINT_DINT UINT64_C(0x0000000000000003)
+#define CIU_DINT_DINT UINT64_C(0x0000ffffffffffff)
-#define CIU_FUSE_XXX_63_2 UINT64_C(0xfffffffffffffffc)
-#define CIU_FUSE_FUSE UINT64_C(0x0000000000000003)
+#define CIU_FUSE_FUSE UINT64_C(0x0000ffffffffffff)
-#define CIU_BIST_XXX_63_4 UINT64_C(0xfffffffffffffff0)
-#define CIU_BIST_BIST UINT64_C(0x000000000000000f)
+#define CIU_BIST_BIST UINT64_C(0x0000ffffffffffff)
#define CIU_SOFT_BIST_XXX_63_1 UINT64_C(0xfffffffffffffffe)
#define CIU_SOFT_BIST_SOFT_BIST UINT64_C(0x0000000000000001)
Index: src/sys/arch/mips/cavium/dev/octeon_dwctwo.c
diff -u src/sys/arch/mips/cavium/dev/octeon_dwctwo.c:1.10 src/sys/arch/mips/cavium/dev/octeon_dwctwo.c:1.11
--- src/sys/arch/mips/cavium/dev/octeon_dwctwo.c:1.10 Sun May 31 04:56:35 2020
+++ src/sys/arch/mips/cavium/dev/octeon_dwctwo.c Fri Jun 19 02:23:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_dwctwo.c,v 1.10 2020/05/31 04:56:35 simonb Exp $ */
+/* $NetBSD: octeon_dwctwo.c,v 1.11 2020/06/19 02:23:43 simonb Exp $ */
/*
* Copyright (c) 2015 Masao Uebayashi <[email protected]>
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_dwctwo.c,v 1.10 2020/05/31 04:56:35 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_dwctwo.c,v 1.11 2020/06/19 02:23:43 simonb Exp $");
#include "opt_octeon.h"
#include "opt_usb.h"
@@ -310,8 +310,7 @@ octeon_dwc2_attach(device_t parent, devi
sc->sc_dwc2.sc_child =
config_found(sc->sc_dwc2.sc_dev, &sc->sc_dwc2.sc_bus, usbctlprint);
- sc->sc_ih = octeon_intr_establish(ffs64(CIU_INTX_SUM0_USB) - 1,
- IPL_VM, dwc2_intr, sc);
+ sc->sc_ih = octeon_intr_establish(CIU_INT_USB, IPL_VM, dwc2_intr, sc);
if (sc->sc_ih == NULL)
panic("can't establish common interrupt\n");
}
Index: src/sys/arch/mips/cavium/dev/octeon_gmx.c
diff -u src/sys/arch/mips/cavium/dev/octeon_gmx.c:1.12 src/sys/arch/mips/cavium/dev/octeon_gmx.c:1.13
--- src/sys/arch/mips/cavium/dev/octeon_gmx.c:1.12 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_gmx.c Fri Jun 19 02:23:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_gmx.c,v 1.12 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_gmx.c,v 1.13 2020/06/19 02:23:43 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_gmx.c,v 1.12 2020/06/18 13:52:08 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_gmx.c,v 1.13 2020/06/19 02:23:43 simonb Exp $");
#include "opt_octeon.h"
@@ -239,9 +239,8 @@ octgmx_attach(device_t parent, device_t
#ifdef CNMAC_DEBUG
octgmx_intr_evcnt_attach(sc);
if (octgmx_intr_drop_ih == NULL)
- octgmx_intr_drop_ih = octeon_intr_establish(
- ffs64(CIU_INTX_SUM0_GMX_DRP) - 1, IPL_NET,
- octgmx_intr_drop, NULL);
+ octgmx_intr_drop_ih = octeon_intr_establish(CIU_INT_GMX_DRP,
+ IPL_NET, octgmx_intr_drop, NULL);
#endif
}
Index: src/sys/arch/mips/cavium/dev/octeon_ipd.c
diff -u src/sys/arch/mips/cavium/dev/octeon_ipd.c:1.4 src/sys/arch/mips/cavium/dev/octeon_ipd.c:1.5
--- src/sys/arch/mips/cavium/dev/octeon_ipd.c:1.4 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_ipd.c Fri Jun 19 02:23:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ipd.c,v 1.4 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_ipd.c,v 1.5 2020/06/19 02:23:43 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c,v 1.4 2020/06/18 13:52:08 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c,v 1.5 2020/06/19 02:23:43 simonb Exp $");
#include "opt_octeon.h"
@@ -96,9 +96,8 @@ octipd_init(struct octipd_attach_args *a
octipd_int_enable(sc, 1);
octipd_intr_evcnt_attach(sc);
if (octipd_intr_drop_ih == NULL)
- octipd_intr_drop_ih = octeon_intr_establish(
- ffs64(CIU_INTX_SUM0_IPD_DRP) - 1, IPL_NET,
- octipd_intr_drop, NULL);
+ octipd_intr_drop_ih = octeon_intr_establish(CIU_INT_IPD_DRP,
+ IPL_NET, octipd_intr_drop, NULL);
__octipd_softc[sc->sc_port] = sc;
#endif /* CNMAC_DEBUG */
}
Index: src/sys/arch/mips/cavium/dev/octeon_mpi.c
diff -u src/sys/arch/mips/cavium/dev/octeon_mpi.c:1.4 src/sys/arch/mips/cavium/dev/octeon_mpi.c:1.5
--- src/sys/arch/mips/cavium/dev/octeon_mpi.c:1.4 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_mpi.c Fri Jun 19 02:23:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_mpi.c,v 1.4 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_mpi.c,v 1.5 2020/06/19 02:23:43 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_mpi.c,v 1.4 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_mpi.c,v 1.5 2020/06/19 02:23:43 simonb Exp $");
#include "opt_octeon.h"
@@ -139,8 +139,7 @@ octmpi_attach(device_t parent, device_t
octmpi_reg_wr(sc, MPI_CFG_OFFSET,
(0x7d << MPI_CFG_CLKDIV_SHIFT) | MPI_CFG_CSENA | MPI_CFG_ENABLE | MPI_CFG_INT_ENA);
/* Enable device interrupts */
- sc->sc_ih = octeon_intr_establish(ffs64(CIU_INTX_SUM0_MPI) - 1,
- IPL_SERIAL, octmpi_intr, sc);
+ sc->sc_ih = octeon_intr_establish(CIU_INT_MPI, IPL_SERIAL, octmpi_intr, sc);
if (sc->sc_ih == NULL)
panic("l2sw: can't establish interrupt\n");
#else
Index: src/sys/arch/mips/cavium/dev/octeon_pci.c
diff -u src/sys/arch/mips/cavium/dev/octeon_pci.c:1.3 src/sys/arch/mips/cavium/dev/octeon_pci.c:1.4
--- src/sys/arch/mips/cavium/dev/octeon_pci.c:1.3 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pci.c Fri Jun 19 02:23:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pci.c,v 1.3 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_pci.c,v 1.4 2020/06/19 02:23:43 simonb Exp $ */
/*
* Copyright (c) 2007, 2008 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_pci.c,v 1.3 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_pci.c,v 1.4 2020/06/19 02:23:43 simonb Exp $");
#include "opt_octeon.h"
@@ -65,8 +65,8 @@ static void
octpci_init(void)
{
#ifdef CNMAC_DEBUG
- octpci_intr_rml_ih = octeon_intr_establish(
- ffs64(CIU_INTX_SUM0_RML) - 1, IPL_NET, octpci_intr_rml, NULL);
+ octpci_intr_rml_ih = octeon_intr_establish( CIU_INT_RML, IPL_NET,
+ octpci_intr_rml, NULL);
#endif
}
Index: src/sys/arch/mips/cavium/dev/octeon_pow.c
diff -u src/sys/arch/mips/cavium/dev/octeon_pow.c:1.7 src/sys/arch/mips/cavium/dev/octeon_pow.c:1.8
--- src/sys/arch/mips/cavium/dev/octeon_pow.c:1.7 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pow.c Fri Jun 19 02:23:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pow.c,v 1.7 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_pow.c,v 1.8 2020/06/19 02:23:43 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_pow.c,v 1.7 2020/06/18 13:52:08 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_pow.c,v 1.8 2020/06/19 02:23:43 simonb Exp $");
#include "opt_octeon.h" /* CNMAC_DEBUG */
@@ -313,7 +313,7 @@ octpow_intr_establish(int group, int lev
pow_ih = malloc(sizeof(*pow_ih), M_DEVBUF, M_WAITOK);
pow_ih->pi_ih = octeon_intr_establish(
- ffs64(CIU_INTX_SUM0_WORKQ_0) - 1 + group,
+ CIU_INT_WORKQ_0 + group,
level,
octpow_intr, pow_ih);
KASSERT(pow_ih->pi_ih != NULL);
Index: src/sys/arch/mips/cavium/dev/octeon_uart.c
diff -u src/sys/arch/mips/cavium/dev/octeon_uart.c:1.7 src/sys/arch/mips/cavium/dev/octeon_uart.c:1.8
--- src/sys/arch/mips/cavium/dev/octeon_uart.c:1.7 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_uart.c Fri Jun 19 02:23:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_uart.c,v 1.7 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_uart.c,v 1.8 2020/06/19 02:23:43 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_uart.c,v 1.7 2020/06/18 13:52:08 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_uart.c,v 1.8 2020/06/19 02:23:43 simonb Exp $");
#include "opt_octeon.h"
@@ -145,8 +145,7 @@ octuart_iobus_attach(device_t parent, de
com_attach_subr(sc_com);
- /* XXX pass intr mask via _attach_args -- uebayasi */
- sc->sc_ih = octeon_intr_establish(ffs64(CIU_INTX_SUM0_UART_0) - 1/* XXX */ + device_unit(self),
+ sc->sc_ih = octeon_intr_establish(CIU_INT_UART_0 + device_unit(self),
IPL_SERIAL, comintr, sc_com);
if (sc->sc_ih == NULL)
panic("%s: can't establish interrupt\n",
