Module Name: src
Committed By: simonb
Date: Tue Jun 23 05:15:33 UTC 2020
Modified Files:
src/sys/arch/mips/cavium: octeonvar.h
src/sys/arch/mips/cavium/dev: octeon_ipd.c octeon_ipdvar.h octeon_pko.c
octeon_pkovar.h octeon_pow.c octeon_powreg.h octeon_powvar.h
Log Message:
Cleanup - mostly removing unused code and defines.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/cavium/octeonvar.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/cavium/dev/octeon_ipd.c \
src/sys/arch/mips/cavium/dev/octeon_powvar.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/cavium/dev/octeon_ipdvar.h \
src/sys/arch/mips/cavium/dev/octeon_pko.c \
src/sys/arch/mips/cavium/dev/octeon_powreg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/cavium/dev/octeon_pkovar.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/cavium/dev/octeon_pow.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/octeonvar.h
diff -u src/sys/arch/mips/cavium/octeonvar.h:1.12 src/sys/arch/mips/cavium/octeonvar.h:1.13
--- src/sys/arch/mips/cavium/octeonvar.h:1.12 Mon Jun 22 02:26:19 2020
+++ src/sys/arch/mips/cavium/octeonvar.h Tue Jun 23 05:15:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeonvar.h,v 1.12 2020/06/22 02:26:19 simonb Exp $ */
+/* $NetBSD: octeonvar.h,v 1.13 2020/06/23 05:15:33 simonb Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -52,18 +52,6 @@
" .set arch=octeon \n"
#define _ASM_EPILOGUE \
" .set pop \n"
-/*
- * subbits = __BITS64_GET(XXX, bits);
- * bits = __BITS64_SET(XXX, subbits);
- */
-#ifndef __BITS64_GET
-#define __BITS64_GET(name, bits) \
- (((uint64_t)(bits) & name) >> name##_SHIFT)
-#endif
-#ifndef __BITS64_SET
-#define __BITS64_SET(name, subbits) \
- (((uint64_t)(subbits) << name##_SHIFT) & name)
-#endif
#ifdef _KERNEL
extern int octeon_core_ver;
@@ -211,22 +199,7 @@ struct octfau_map {
#define OCTEON_POW_QOS_XXX_6 6
#define OCTEON_POW_QOS_XXX_7 7
-#define OCTEON_POW_GROUP_PIP 0
-#define OCTEON_POW_GROUP_XXX_1 1
-#define OCTEON_POW_GROUP_XXX_2 2
-#define OCTEON_POW_GROUP_XXX_3 3
-#define OCTEON_POW_GROUP_XXX_4 4
-#define OCTEON_POW_GROUP_XXX_5 5
-#define OCTEON_POW_GROUP_XXX_6 6
-#define OCTEON_POW_GROUP_CORE1_SEND 7
-#define OCTEON_POW_GROUP_CORE1_TASK_0 8
-#define OCTEON_POW_GROUP_CORE1_TASK_1 9
-#define OCTEON_POW_GROUP_CORE1_TASK_2 10
-#define OCTEON_POW_GROUP_CORE1_TASK_3 11
-#define OCTEON_POW_GROUP_CORE1_TASK_4 12
-#define OCTEON_POW_GROUP_CORE1_TASK_5 13
-#define OCTEON_POW_GROUP_CORE1_TASK_6 14
-#define OCTEON_POW_GROUP_CORE1_TASK_7 15
+#define OCTEON_POW_GROUP_MAX 16
#ifdef _KERNEL
extern struct octeon_config octeon_configuration;
@@ -305,14 +278,6 @@ void mips_cp0_cvmctl_write(uint64_t);
#define OCTEON_SYNC OCTEON_SYNCCOMMON(sync)
#define OCTEON_SYNCWS OCTEON_SYNCCOMMON(syncws)
#define OCTEON_SYNCS OCTEON_SYNCCOMMON(syncs)
-/* XXX backward compatibility */
-#if 1
-#define OCT_SYNCIOBDMA OCTEON_SYNCIOBDMA
-#define OCT_SYNCW OCTEON_SYNCW
-#define OCT_SYNC OCTEON_SYNC
-#define OCT_SYNCWS OCTEON_SYNCWS
-#define OCT_SYNCS OCTEON_SYNCS
-#endif
/* octeon core does not use cca to determine cacheability */
#define OCTEON_CCA_NONE UINT64_C(0)
@@ -329,14 +294,6 @@ octeon_xkphys_write_8(paddr_t address, u
mips3_sd(MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, address), value);
}
-/* XXX backward compatibility */
-#if 1
-#define octeon_read_csr(address) \
- octeon_xkphys_read_8(address)
-#define octeon_write_csr(address, value) \
- octeon_xkphys_write_8(address, value)
-#endif
-
static __inline void
octeon_iobdma_write_8(uint64_t value)
{
@@ -347,72 +304,15 @@ octeon_iobdma_write_8(uint64_t value)
static __inline uint64_t
octeon_cvmseg_read_8(size_t offset)
{
+
return octeon_xkphys_read_8(OCTEON_CVMSEG_LM + offset);
}
static __inline void
octeon_cvmseg_write_8(size_t offset, uint64_t value)
{
- octeon_xkphys_write_8(OCTEON_CVMSEG_LM + offset, value);
-}
-
-/* XXX */
-static __inline uint32_t
-octeon_disable_interrupt(uint32_t *new)
-{
- uint32_t s, tmp;
-
- __asm __volatile (
- _ASM_PROLOGUE
- " mfc0 %[s], $12 \n"
- " and %[tmp], %[s], ~1 \n"
- " mtc0 %[tmp], $12 \n"
- _ASM_EPILOGUE
- : [s]"=&r"(s), [tmp]"=&r"(tmp));
- if (new)
- *new = tmp;
- return s;
-}
-
-/* XXX */
-static __inline void
-octeon_restore_status(uint32_t s)
-{
- __asm __volatile (
- _ASM_PROLOGUE
- " mtc0 %[s], $12 \n"
- _ASM_EPILOGUE
- :: [s]"r"(s));
-}
-static __inline uint64_t
-octeon_get_cycles(void)
-{
-#if defined(__mips_o32)
- uint32_t s, lo, hi;
-
- s = octeon_disable_interrupt((void *)0);
- __asm __volatile (
- _ASM_PROLOGUE_MIPS64
- " dmfc0 %[lo], $9, 6 \n"
- " add %[hi], %[lo], $0 \n"
- " srl %[hi], 32 \n"
- " sll %[lo], 32 \n"
- " srl %[lo], 32 \n"
- _ASM_EPILOGUE
- : [lo]"=&r"(lo), [hi]"=&r"(hi));
- octeon_restore_status(s);
- return ((uint64_t)hi << 32) + (uint64_t)lo;
-#else
- uint64_t tmp;
-
- __asm __volatile (
- _ASM_PROLOGUE_MIPS64
- " dmfc0 %[tmp], $9, 6 \n"
- _ASM_EPILOGUE
- : [tmp]"=&r"(tmp));
- return tmp;
-#endif
+ octeon_xkphys_write_8(OCTEON_CVMSEG_LM + offset, value);
}
#endif /* _MIPS_OCTEON_OCTEONVAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_ipd.c
diff -u src/sys/arch/mips/cavium/dev/octeon_ipd.c:1.6 src/sys/arch/mips/cavium/dev/octeon_ipd.c:1.7
--- src/sys/arch/mips/cavium/dev/octeon_ipd.c:1.6 Mon Jun 22 02:26:20 2020
+++ src/sys/arch/mips/cavium/dev/octeon_ipd.c Tue Jun 23 05:15:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ipd.c,v 1.6 2020/06/22 02:26:20 simonb Exp $ */
+/* $NetBSD: octeon_ipd.c,v 1.7 2020/06/23 05:15:33 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,11 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c,v 1.6 2020/06/22 02:26:20 simonb Exp $");
-
-#include "opt_octeon.h"
-
-#include "opt_octeon.h"
+__KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c,v 1.7 2020/06/23 05:15:33 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -208,55 +204,6 @@ octipd_offload(uint64_t word2, void *dat
*rcflags = cflags;
}
-int
-octipd_red(struct octipd_softc *sc, uint64_t pass_thr, uint64_t drop_thr)
-{
-#if defined(CNMAC_IPD_RED)
- /*
- * no receive problem workaround.
- * if not set IPD RED pramaters,
- * may become unable to receive packet
- * on media mismatch environment
- * of self media 100-half duplex.
- */
- uint64_t red_marks;
- uint64_t red_param;
- uint64_t red_port;
-
- red_marks = drop_thr << 32 /* XXX */ | pass_thr;
- _IPD_WR8(sc, IPD_QOS0_RED_MARKS_OFFSET, red_marks);
- _IPD_WR8(sc, IPD_QOS1_RED_MARKS_OFFSET, red_marks);
- _IPD_WR8(sc, IPD_QOS2_RED_MARKS_OFFSET, red_marks);
- _IPD_WR8(sc, IPD_QOS3_RED_MARKS_OFFSET, red_marks);
- _IPD_WR8(sc, IPD_QOS4_RED_MARKS_OFFSET, red_marks);
- _IPD_WR8(sc, IPD_QOS5_RED_MARKS_OFFSET, red_marks);
- _IPD_WR8(sc, IPD_QOS6_RED_MARKS_OFFSET, red_marks);
- _IPD_WR8(sc, IPD_QOS7_RED_MARKS_OFFSET, red_marks);
- red_param =
- ((255ull << 24 /* XXX */) / (pass_thr - drop_thr)) |
- 1ull << 32 /* XXX */ |
- 255ull << 40 /* XXX */ |
- 1ull << 48 /* XXX */;
- _IPD_WR8(sc, IPD_RED_QUE0_PARAM_OFFSET, red_param);
- _IPD_WR8(sc, IPD_RED_QUE1_PARAM_OFFSET, red_param);
- _IPD_WR8(sc, IPD_RED_QUE2_PARAM_OFFSET, red_param);
- _IPD_WR8(sc, IPD_RED_QUE3_PARAM_OFFSET, red_param);
- _IPD_WR8(sc, IPD_RED_QUE4_PARAM_OFFSET, red_param);
- _IPD_WR8(sc, IPD_RED_QUE5_PARAM_OFFSET, red_param);
- _IPD_WR8(sc, IPD_RED_QUE6_PARAM_OFFSET, red_param);
- _IPD_WR8(sc, IPD_RED_QUE7_PARAM_OFFSET, red_param);
-
- _IPD_WR8(sc, IPD_BP_PRT_RED_END_OFFSET, 0);
-
- red_port = 0xfffffffffull |
- 10000ull << 36 /* XXX */ |
- 10000ull << 50 /* XXX */;
- _IPD_WR8(sc, IPD_RED_PORT_ENABLE_OFFSET, red_port);
-#endif
-
- return 0;
-}
-
void
octipd_sub_port_fcs(struct octipd_softc *sc, int enable)
{
@@ -264,8 +211,8 @@ octipd_sub_port_fcs(struct octipd_softc
sub_port_fcs = _IPD_RD8(sc, IPD_SUB_PORT_FCS_OFFSET);
if (enable == 0)
- CLR(sub_port_fcs, 1 << sc->sc_port);
+ CLR(sub_port_fcs, __BIT(sc->sc_port));
else
- SET(sub_port_fcs, 1 << sc->sc_port);
+ SET(sub_port_fcs, __BIT(sc->sc_port));
_IPD_WR8(sc, IPD_SUB_PORT_FCS_OFFSET, sub_port_fcs);
}
Index: src/sys/arch/mips/cavium/dev/octeon_powvar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_powvar.h:1.6 src/sys/arch/mips/cavium/dev/octeon_powvar.h:1.7
--- src/sys/arch/mips/cavium/dev/octeon_powvar.h:1.6 Mon Jun 22 02:26:20 2020
+++ src/sys/arch/mips/cavium/dev/octeon_powvar.h Tue Jun 23 05:15:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_powvar.h,v 1.6 2020/06/22 02:26:20 simonb Exp $ */
+/* $NetBSD: octeon_powvar.h,v 1.7 2020/06/23 05:15:33 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -50,6 +50,8 @@
#define POW_WAIT 1
#define POW_NO_WAIT 0
+#define POW_WORKQ_IRQ(group) (group)
+
/* XXX */
struct octpow_softc {
device_t sc_dev;
@@ -65,17 +67,13 @@ struct octpow_attach_args {
bus_space_tag_t aa_regt;
};
-void octpow_config(struct octpow_softc *, int);
-void *octpow_intr_establish(int, int,
- void (*)(void *, uint64_t *),
- void (*)(int *, int *, uint64_t, void *),
- void *);
-void octpow_error_int_enable(void *, int);
-uint64_t octpow_error_int_summary(void *);
-int octpow_ring_reduce(void *);
-int octpow_ring_grow(void *);
-int octpow_ring_size(void);
-int octpow_ring_intr(void);
+void octpow_config(struct octpow_softc *, int);
+void octpow_error_int_enable(void *, int);
+uint64_t octpow_error_int_summary(void *);
+int octpow_ring_reduce(void *);
+int octpow_ring_grow(void *);
+int octpow_ring_size(void);
+int octpow_ring_intr(void);
#define _POW_RD8(sc, off) \
bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
@@ -107,91 +105,6 @@ octpow_ops_get_work_load(
return octeon_xkphys_read_8(ptr);
}
-/* POW Status Loads */
-
-/*
- * a) get_cur == 0, get_wqp == 0 (pend_tag)
- * b) get_cur == 0, get_wqp == 1 (pend_wqp)
- * c) get_cur == 1, get_wqp == 0, get_rev == 0 (cur_tag_next)
- * d) get_cur == 1, get_wqp == 0, get_rev == 1 (cur_tag_prev)
- * e) get_cur == 1, get_wqp == 1, get_rev == 0 (cur_wqp_next)
- * f) get_cur == 1, get_wqp == 1, get_rev == 1 (cur_wqp_prev)
- */
-
-static __inline uint64_t
-octpow_ops_pow_status(
- int coreid, /* 0-15 */
- int get_rev, /* 0-1 */
- int get_cur, /* 0-1 */
- int get_wqp) /* 0-1 */
-{
- uint64_t ptr =
- OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_STATUS_LOAD) |
- __SHIFTIN(coreid, POW_STATUS_LOAD_COREID) |
- __SHIFTIN(get_rev, POW_STATUS_LOAD_GET_REV) |
- __SHIFTIN(get_cur, POW_STATUS_LOAD_GET_CUR) |
- __SHIFTIN(get_wqp, POW_STATUS_LOAD_GET_WQP);
-
- return octeon_xkphys_read_8(ptr);
-}
-
-/* POW Memory Loads */
-
-/*
- * a) get_des == 0, get_wqp == 0 (tag)
- * b) get_des == 0, get_wqp == 1 (wqe)
- * c) get_des == 1 (desched)
- */
-
-static __inline uint64_t
-octpow_ops_pow_memory(
- int index, /* 0-2047 */
- int get_des, /* 0-1 */
- int get_wqp) /* 0-1 */
-{
- uint64_t ptr =
- OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_MEMORY_LOAD) |
- __SHIFTIN(index, POW_MEMORY_LOAD_INDEX) |
- __SHIFTIN(get_des, POW_MEMORY_LOAD_GET_DES) |
- __SHIFTIN(get_wqp, POW_MEMORY_LOAD_GET_WQP);
-
- return octeon_xkphys_read_8(ptr);
-}
-
-/* POW Index/Pointer Loads */
-
-/*
- * a) get_rmt == 0, get_des_get_tail == 0
- * b) get_rmt == 0, get_des_get_tail == 1
- * c) get_rmt == 1, get_des_get_tail == 0
- * d) get_rmt == 1, get_des_get_tail == 1
- */
-
-static __inline uint64_t
-octpow_ops_pow_idxptr(
- int qosgrp, /* 0-7 */
- int get_des_get_tail, /* 0-1 */
- int get_rmt) /* 0-1 */
-{
- uint64_t ptr =
- OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_IDXPTR_LOAD) |
- __SHIFTIN(qosgrp, POW_IDXPTR_LOAD_QOSGRP) |
- __SHIFTIN(get_des_get_tail, POW_IDXPTR_LOAD_GET_DES_GET_TAIL) |
- __SHIFTIN(get_rmt, POW_IDXPTR_LOAD_GET_RMT);
-
- return octeon_xkphys_read_8(ptr);
-}
-
-/* NULL_RD Loads */
-
-static __inline uint64_t
-octpow_ops_null_rd_load(void)
-{
- uint64_t ptr = OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_NULL_RD);
-
- return octeon_xkphys_read_8(ptr);
-}
-
/* IOBDMA Operations */
/* ``subdid'' values are inverted between ``get_work_addr'' and ``null_read_id'' */
@@ -406,6 +319,40 @@ octpow_ops_nop(void)
0); /* tag (not used for NOP) */
}
+/*
+ * Check if there is a pending POW tag switch.
+ */
+static __inline int
+octpow_tag_sw_pending(void)
+{
+ int result;
+
+ /*
+ * "RDHWR rt, $30" returns:
+ * 0 => pending bit is set
+ * 1 => pending bit is clear
+ */
+
+ __asm volatile (
+ " .set push\n"
+ " .set noreorder\n"
+ " .set arch=mips64r2\n"
+ " rdhwr %0, $30\n"
+ " .set pop\n"
+ : "=r" (result));
+ return result == 0;
+}
+
+/*
+ * Wait until there is no pending POW tag switch.
+ */
+static inline void
+octpow_tag_sw_wait(void)
+{
+ while (octpow_tag_sw_pending())
+ continue;
+}
+
/* -------------------------------------------------------------------------- */
/*
@@ -432,8 +379,7 @@ octpow_work_response_async(uint64_t scra
return NULL;
#ifdef __mips_n32
KASSERT(addr < MIPS_PHYS_MASK);
- //if (addr < MIPS_PHYS_MASK)
- return (uint64_t *)MIPS_PHYS_TO_KSEG0(addr);
+ return (uint64_t *)MIPS_PHYS_TO_KSEG0(addr);
#else
return (uint64_t *)MIPS_PHYS_TO_XKPHYS_CACHED(addr);
#endif
@@ -463,19 +409,4 @@ octpow_config_int_pc_rate(struct octpow_
octpow_config_int_pc(sc, sc->sc_int_pc_base / rate);
}
-/* wait until ready */
-static __inline void
-octpow_tag_sw_wait(void)
-{
- __asm __volatile (
- " .set push \n"
- " .set noreorder \n"
- " .set arch=octeon \n"
- "1: rdhwr $2, $30 \n"
- " beqz $2, 1b \n"
- " nop \n"
- " .set pop \n"
- );
-}
-
-#endif /* _OCTEON_POWVAR_H_ */
+#endif /* !_OCTEON_POWVAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_ipdvar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_ipdvar.h:1.4 src/sys/arch/mips/cavium/dev/octeon_ipdvar.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_ipdvar.h:1.4 Mon Jun 22 02:26:20 2020
+++ src/sys/arch/mips/cavium/dev/octeon_ipdvar.h Tue Jun 23 05:15:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ipdvar.h,v 1.4 2020/06/22 02:26:20 simonb Exp $ */
+/* $NetBSD: octeon_ipdvar.h,v 1.5 2020/06/23 05:15:33 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -49,7 +49,6 @@ struct octipd_attach_args {
void octipd_init(struct octipd_attach_args *, struct octipd_softc **);
int octipd_enable(struct octipd_softc *);
int octipd_config(struct octipd_softc *);
-int octipd_red(struct octipd_softc *, uint64_t, uint64_t);
void octipd_sub_port_fcs(struct octipd_softc *, int);
void octipd_offload(uint64_t, void *, int *);
Index: src/sys/arch/mips/cavium/dev/octeon_pko.c
diff -u src/sys/arch/mips/cavium/dev/octeon_pko.c:1.4 src/sys/arch/mips/cavium/dev/octeon_pko.c:1.5
--- src/sys/arch/mips/cavium/dev/octeon_pko.c:1.4 Mon Jun 22 02:26:20 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pko.c Tue Jun 23 05:15:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pko.c,v 1.4 2020/06/22 02:26:20 simonb Exp $ */
+/* $NetBSD: octeon_pko.c,v 1.5 2020/06/23 05:15:33 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,9 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_pko.c,v 1.4 2020/06/22 02:26:20 simonb Exp $");
-
-#include "opt_octeon.h"
+__KERNEL_RCSID(0, "$NetBSD: octeon_pko.c,v 1.5 2020/06/23 05:15:33 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -42,6 +40,8 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_pko.c
#include <mips/cavium/dev/octeon_pkoreg.h>
#include <mips/cavium/dev/octeon_pkovar.h>
+static inline void octpko_op_store(uint64_t, uint64_t);
+
#define _PKO_RD8(sc, off) \
bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
#define _PKO_WR8(sc, off, v) \
@@ -91,25 +91,13 @@ octpko_enable(struct octpko_softc *sc)
return 0;
}
-#if 0
-void
-octpko_reset(octpko_softc *sc)
-{
- uint64_t reg_flags;
-
- reg_flags = _PKO_RD8(sc, PKO_REG_FLAGS_OFFSET);
- SET(reg_flags, PKO_REG_FLAGS_RESET);
- _PKO_WR8(sc, PKO_REG_FLAGS_OFFSET, reg_flags);
-}
-#endif
-
void
octpko_config(struct octpko_softc *sc)
{
uint64_t reg_cmd_buf = 0;
- SET(reg_cmd_buf, (sc->sc_cmd_buf_pool << 20) & PKO_REG_CMD_BUF_POOL);
- SET(reg_cmd_buf, sc->sc_cmd_buf_size & PKO_REG_CMD_BUF_SIZE);
+ SET(reg_cmd_buf, __SHIFTIN(sc->sc_cmd_buf_pool, PKO_REG_CMD_BUF_POOL));
+ SET(reg_cmd_buf, __SHIFTIN(sc->sc_cmd_buf_size, PKO_REG_CMD_BUF_SIZE));
_PKO_WR8(sc, PKO_REG_CMD_BUF_OFFSET, reg_cmd_buf);
}
@@ -125,10 +113,9 @@ octpko_port_enable(struct octpko_softc *
/* XXX assume one queue maped one port */
/* Enable packet output by enabling all queues for this port */
mem_queue_qos = 0;
- SET(mem_queue_qos, ((uint64_t)sc->sc_port << 7) & PKO_MEM_QUEUE_QOS_PID);
- SET(mem_queue_qos, sc->sc_port & PKO_MEM_QUEUE_QOS_QID);
- SET(mem_queue_qos, ((enable ? 0xffULL : 0x00ULL) << 53) &
- PKO_MEM_QUEUE_QOS_QOS_MASK);
+ SET(mem_queue_qos, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_QOS_PID));
+ SET(mem_queue_qos, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_QOS_QID));
+ SET(mem_queue_qos, enable ? PKO_MEM_QUEUE_QOS_QOS_MASK : 0);
_PKO_WR8(sc, PKO_REG_READ_IDX_OFFSET, reg_read_idx);
_PKO_WR8(sc, PKO_MEM_QUEUE_QOS_OFFSET, mem_queue_qos);
@@ -155,11 +142,11 @@ octpko_port_config(struct octpko_softc *
/* assume one queue maped one port */
mem_queue_ptrs = 0;
SET(mem_queue_ptrs, PKO_MEM_QUEUE_PTRS_TAIL);
- SET(mem_queue_ptrs, ((uint64_t)0 << 13) & PKO_MEM_QUEUE_PTRS_IDX);
- SET(mem_queue_ptrs, ((uint64_t)sc->sc_port << 7) & PKO_MEM_QUEUE_PTRS_PID);
- SET(mem_queue_ptrs, sc->sc_port & PKO_MEM_QUEUE_PTRS_QID);
- SET(mem_queue_ptrs, ((uint64_t)0xff << 53) & PKO_MEM_QUEUE_PTRS_QOS_MASK);
- SET(mem_queue_ptrs, ((uint64_t)buf_ptr << 17) & PKO_MEM_QUEUE_PTRS_BUF_PTR);
+ SET(mem_queue_ptrs, __SHIFTIN(0, PKO_MEM_QUEUE_PTRS_IDX));
+ SET(mem_queue_ptrs, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_PTRS_PID));
+ SET(mem_queue_ptrs, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_PTRS_QID));
+ SET(mem_queue_ptrs, __SHIFTIN(0xff, PKO_MEM_QUEUE_PTRS_QOS_MASK));
+ SET(mem_queue_ptrs, __SHIFTIN(buf_ptr, PKO_MEM_QUEUE_PTRS_BUF_PTR));
OCTEON_SYNCW;
_PKO_WR8(sc, PKO_MEM_QUEUE_PTRS_OFFSET, mem_queue_ptrs);
Index: src/sys/arch/mips/cavium/dev/octeon_powreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_powreg.h:1.4 src/sys/arch/mips/cavium/dev/octeon_powreg.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_powreg.h:1.4 Mon Jun 22 12:26:11 2020
+++ src/sys/arch/mips/cavium/dev/octeon_powreg.h Tue Jun 23 05:15:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_powreg.h,v 1.4 2020/06/22 12:26:11 simonb Exp $ */
+/* $NetBSD: octeon_powreg.h,v 1.5 2020/06/23 05:15:33 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -35,8 +35,7 @@
/* ---- register addresses */
-#define POW_PP_GRP_MSK0 UINT64_C(0x0001670000000000)
-#define POW_PP_GRP_MSK1 UINT64_C(0x0001670000000008)
+#define POW_PP_GRP_MSK(core) (UINT64_C(0x0001670000000000) + (core) * 8)
#define POW_WQ_INT_THR0 UINT64_C(0x0001670000000080)
#define POW_WQ_INT_THR1 UINT64_C(0x0001670000000088)
#define POW_WQ_INT_THR2 UINT64_C(0x0001670000000090)
@@ -131,8 +130,7 @@
#define POW_BASE UINT64_C(0x0001670000000000)
#define POW_SIZE UINT64_C(0x400)
-#define POW_PP_GRP_MSK0_OFFSET UINT64_C(0x0)
-#define POW_PP_GRP_MSK1_OFFSET UINT64_C(0x8)
+#define POW_PP_GRP_MSK_OFFSET(core) (UINT64_C(0) + (core) * 8)
#define POW_WQ_INT_THR0_OFFSET UINT64_C(0x80)
#define POW_WQ_INT_THR1_OFFSET UINT64_C(0x88)
#define POW_WQ_INT_THR2_OFFSET UINT64_C(0x90)
Index: src/sys/arch/mips/cavium/dev/octeon_pkovar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_pkovar.h:1.5 src/sys/arch/mips/cavium/dev/octeon_pkovar.h:1.6
--- src/sys/arch/mips/cavium/dev/octeon_pkovar.h:1.5 Mon Jun 22 02:26:20 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pkovar.h Tue Jun 23 05:15:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pkovar.h,v 1.5 2020/06/22 02:26:20 simonb Exp $ */
+/* $NetBSD: octeon_pkovar.h,v 1.6 2020/06/23 05:15:33 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -138,7 +138,7 @@ octpko_op_store(uint64_t args, uint64_t
addr = OCTEON_ADDR_IO_DID(PKO_MAJOR_DID, PKO_SUB_DID) | args;
/* XXX */
OCTEON_SYNCW;
- octeon_write_csr(addr, value);
+ octeon_xkphys_write_8(addr, value);
}
static __inline void
Index: src/sys/arch/mips/cavium/dev/octeon_pow.c
diff -u src/sys/arch/mips/cavium/dev/octeon_pow.c:1.9 src/sys/arch/mips/cavium/dev/octeon_pow.c:1.10
--- src/sys/arch/mips/cavium/dev/octeon_pow.c:1.9 Mon Jun 22 02:26:20 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pow.c Tue Jun 23 05:15:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pow.c,v 1.9 2020/06/22 02:26:20 simonb Exp $ */
+/* $NetBSD: octeon_pow.c,v 1.10 2020/06/23 05:15:33 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,195 +27,26 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_pow.c,v 1.9 2020/06/22 02:26:20 simonb Exp $");
-
-#include "opt_octeon.h" /* CNMAC_DEBUG */
+__KERNEL_RCSID(0, "$NetBSD: octeon_pow.c,v 1.10 2020/06/23 05:15:33 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
-#include <sys/types.h>
-#include <sys/kernel.h> /* hz */
-#include <sys/malloc.h>
-#include <sys/device.h> /* evcnt */
-#include <sys/syslog.h> /* evcnt */
-
-#include <sys/bus.h>
#include <mips/include/locore.h>
#include <mips/cavium/octeonvar.h>
#include <mips/cavium/include/iobusvar.h>
-#include <mips/cavium/dev/octeon_ciureg.h> /* XXX */
#include <mips/cavium/dev/octeon_powreg.h>
#include <mips/cavium/dev/octeon_powvar.h>
-/* XXX ensure assertion */
-#if !defined(DIAGNOSTIC)
-#define DIAGNOSTIC
-#endif
-
-extern int ipflow_fastforward_disable_flags;
-
-struct octpow_intr_handle {
- void *pi_ih;
- struct octpow_softc *pi_sc;
- int pi_group;
- void (*pi_cb)(void *, uint64_t *);
- void *pi_data;
-};
-
void octpow_bootstrap(struct octeon_config *);
static void octpow_init(struct octpow_softc *);
static void octpow_init_regs(struct octpow_softc *);
-static inline int octpow_tag_sw_poll(void) __unused;
-static inline void octpow_tag_sw_wait(void);
-static inline void octpow_config_int_pc(struct octpow_softc *, int);
-static inline void octpow_config_int(struct octpow_softc *, int, uint64_t,
- uint64_t, uint64_t);
-static inline void octpow_intr_work(struct octpow_softc *,
- struct octpow_intr_handle *, int);
-static int octpow_intr(void *);
+static inline void octpow_config_int(struct octpow_softc *, int,
+ uint64_t, uint64_t, uint64_t);
-/* XXX */
struct octpow_softc octpow_softc;
-/*
- * XXX: parameter tuning is needed: see files.octeon
- */
-#ifndef CNMAC_RING_MAX
-#define CNMAC_RING_MAX 512
-#endif
-#ifndef CNMAC_RING_MIN
-#define CNMAC_RING_MIN 1
-#endif
-
-#ifdef CNMAC_INTR_FEEDBACK_RING
-int max_recv_cnt = CNMAC_RING_MAX;
-int min_recv_cnt = CNMAC_RING_MIN;
-int recv_cnt = CNMAC_RING_MIN;
-int int_rate = 1;
-#endif
-
-/* -------------------------------------------------------------------------- */
-
-/* ---- utility functions */
-
-
-/* ---- status by coreid */
-
-static inline uint64_t
-octpow_status_by_coreid_pend_tag(int coreid)
-{
- return octpow_ops_pow_status(coreid, 0, 0, 0);
-}
-
-static inline uint64_t
-octpow_status_by_coreid_pend_wqp(int coreid)
-{
- return octpow_ops_pow_status(coreid, 0, 0, 1);
-}
-
-static inline uint64_t
-octpow_status_by_coreid_cur_tag_next(int coreid)
-{
- return octpow_ops_pow_status(coreid, 0, 1, 0);
-}
-
-static inline uint64_t
-octpow_status_by_coreid_cur_tag_prev(int coreid)
-{
- return octpow_ops_pow_status(coreid, 1, 1, 0);
-}
-
-static inline uint64_t
-octpow_status_by_coreid_cur_wqp_next(int coreid)
-{
- return octpow_ops_pow_status(coreid, 0, 1, 1);
-}
-
-static inline uint64_t
-octpow_status_by_coreid_cur_wqp_prev(int coreid)
-{
- return octpow_ops_pow_status(coreid, 1, 1, 1);
-}
-
-/* ---- status by index */
-
-static inline uint64_t
-octpow_status_by_index_tag(int index)
-{
- return octpow_ops_pow_memory(index, 0, 0);
-}
-
-static inline uint64_t
-octpow_status_by_index_wqp(int index)
-{
- return octpow_ops_pow_memory(index, 0, 1);
-}
-
-static inline uint64_t
-octpow_status_by_index_desched(int index)
-{
- return octpow_ops_pow_memory(index, 1, 0);
-}
-
-/* ---- status by qos level */
-
-static inline uint64_t
-octpow_status_by_qos_free_loc(int qos)
-{
- return octpow_ops_pow_idxptr(qos, 0, 0);
-}
-
-/* ---- status by desched group */
-
-static inline uint64_t
-octpow_status_by_grp_nosched_des(int grp)
-{
- return octpow_ops_pow_idxptr(grp, 0, 1);
-}
-
-/* ---- status by memory input queue */
-
-static inline uint64_t
-octpow_status_by_queue_remote_head(int queue)
-{
- return octpow_ops_pow_idxptr(queue, 1, 0);
-}
-
-static inline uint64_t
-octpow_status_by_queue_remote_tail(int queue)
-{
- return octpow_ops_pow_idxptr(queue, 1, 0);
-}
-
-/* ---- tag switch */
-
-/*
- * "RDHWR rt, $30" returns:
- * 0 => pending bit is set
- * 1 => pending bit is clear
- */
-
-/* return 1 if pending bit is clear (ready) */
-static inline int
-octpow_tag_sw_poll(void)
-{
- uint64_t result;
-
- /* XXX O32 */
- __asm __volatile (
- " .set push \n"
- " .set noreorder \n"
- " .set arch=octeon \n"
- " rdhwr %[result], $30 \n"
- " .set pop \n"
- : [result]"=r"(result)
- );
- /* XXX O32 */
- return (int)result;
-}
-
/* -------------------------------------------------------------------------- */
/* ---- initialization and configuration */
@@ -266,30 +97,6 @@ octpow_config(struct octpow_softc *sc, i
0x00); /* IQ */
}
-void *
-octpow_intr_establish(int group, int level, void (*cb)(void *, uint64_t *),
- void (*fcb)(int*, int *, uint64_t, void *), void *data)
-{
- struct octpow_intr_handle *pow_ih;
-
- KASSERT(group >= 0);
- KASSERT(group < 16);
-
- pow_ih = malloc(sizeof(*pow_ih), M_DEVBUF, M_WAITOK);
- pow_ih->pi_ih = octeon_intr_establish(
- CIU_INT_WORKQ_0 + group,
- level,
- octpow_intr, pow_ih);
- KASSERT(pow_ih->pi_ih != NULL);
-
- pow_ih->pi_sc = &octpow_softc; /* XXX */
- pow_ih->pi_group = group;
- pow_ih->pi_cb = cb;
- pow_ih->pi_data = data;
-
- return pow_ih;
-}
-
void
octpow_init(struct octpow_softc *sc)
{
@@ -309,158 +116,3 @@ octpow_init_regs(struct octpow_softc *sc
if (status != 0)
panic("can't map %s space", "pow register");
}
-
-/* -------------------------------------------------------------------------- */
-
-/* ---- interrupt handling */
-
-/*
- * Interrupt handling by fixed count, following Cavium's SDK code.
- *
- * XXX the fixed count (MAX_RX_CNT) could be changed dynamically?
- *
- * XXX this does not utilize "tag switch" very well
- */
-/*
- * usually all packet receive
- */
-#define MAX_RX_CNT 0x7fffffff
-
-static inline void
-octpow_intr_work(struct octpow_softc *sc, struct octpow_intr_handle *pow_ih,
- int recv_limit)
-{
- uint64_t *work;
- uint64_t count = 0;
-
- _POW_WR8(sc, POW_PP_GRP_MSK0_OFFSET, __BIT(pow_ih->pi_group));
-
- for (count = 0; count < recv_limit; count++) {
- octpow_tag_sw_wait();
- octpow_work_request_async(
- OCTEON_CVMSEG_OFFSET(csm_pow_intr), POW_NO_WAIT);
- work = (uint64_t *)octpow_work_response_async(
- OCTEON_CVMSEG_OFFSET(csm_pow_intr));
- if (work == NULL)
- break;
- (*pow_ih->pi_cb)(pow_ih->pi_data, work);
- }
-}
-
-static int
-octpow_intr(void *data)
-{
- struct octpow_intr_handle *pow_ih = data;
- struct octpow_softc *sc = pow_ih->pi_sc;
- uint64_t wq_int_mask = __BIT(pow_ih->pi_group);
-
-#ifdef CNMAC_INTR_FEEDBACK_RING
- octpow_intr_work(sc, pow_ih, recv_cnt);
-#else
- octpow_intr_work(sc, pow_ih, INT_MAX);
-#endif /* CNMAC_INTR_FEEDBACK_RING */
-
- _POW_WR8(sc, POW_WQ_INT_OFFSET,
- __SHIFTIN(wq_int_mask, POW_WQ_INT_WQ_INT));
- return 1;
-}
-
-#ifdef CNMAC_INTR_FEEDBACK_RING
-int
-octpow_ring_reduce(void *arg)
-{
- struct octpow_softc *sc = arg;
- int new, newi;
- int s;
-
-#if 0
- if (ipflow_fastforward_disable_flags == 0) {
- newi = int_rate = 1;
- octpow_config_int_pc_rate(sc, int_rate);
- return recv_cnt;
- }
-#endif
-
- new = recv_cnt / 2;
- if (new < min_recv_cnt) {
- newi = int_rate << 1;
- if (newi > 128) {
- newi = 128;
-#ifdef POW_DEBUG
- log(LOG_DEBUG,
- "Min intr rate.\n");
-#endif
- new = min_recv_cnt;
- }
- else {
- log(LOG_DEBUG,
- "pow interrupt rate optimized %d->%d.\n",
- int_rate, newi);
- int_rate = newi;
- octpow_config_int_pc_rate(sc, int_rate);
- new = max_recv_cnt;
- }
- }
-
- s = splhigh(); /* XXX */
- recv_cnt = new;
- splx(s);
-
- return new;
-}
-
-int
-octpow_ring_grow(void *arg)
-{
- struct octpow_softc *sc = arg;
- int new, newi;
- int s;
-
-#if 0
- if (ipflow_fastforward_disable_flags == 0) {
- newi = int_rate = 1;
- octpow_config_int_pc_rate(sc, int_rate);
- return recv_cnt;
- }
-#endif
-
- new = recv_cnt + 1;
- if (new > max_recv_cnt) {
- newi = int_rate >> 1;
- if (newi <= 0) {
- newi = 1;
-#ifdef POW_DEBUG
- log(LOG_DEBUG,
- "Max intr rate.\n");
-#endif
- new = max_recv_cnt;
- }
- else {
- log(LOG_DEBUG,
- "pow interrupt rate optimized %d->%d.\n",
- int_rate, newi);
- int_rate = newi;
- octpow_config_int_pc_rate(sc, int_rate);
- new = min_recv_cnt;
- }
- }
-
- s = splhigh(); /* XXX */
- recv_cnt = new;
- splx(s);
-
- return new;
-}
-
-int
-octpow_ring_size(void)
-{
- return recv_cnt;
-}
-
-int
-octpow_ring_intr(void)
-{
- return int_rate;
-}
-#endif /* CNMAC_INTR_FEEDBACK_RING */
