Module Name: src
Committed By: jmcneill
Date: Sun Oct 12 13:07:45 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h awin_usb.c
Log Message:
A31 USB support
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/allwinner/awin_reg.h
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/allwinner/awin_usb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.29 src/sys/arch/arm/allwinner/awin_reg.h:1.30
--- src/sys/arch/arm/allwinner/awin_reg.h:1.29 Sun Oct 12 12:14:43 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Sun Oct 12 13:07:45 2014
@@ -1718,6 +1718,10 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_CPU_AXI_CFG_REG 0x0050
+#define AWIN_A31_AHB_RESET0_REG 0x02C0
+#define AWIN_A31_AHB_RESET1_REG 0x02C4
+#define AWIN_A31_AHB_RESET2_REG 0x02C8
+
#define AWIN_A31_CPUCFG_RST_CTRL_CORE_RESET __BIT(1)
#define AWIN_A31_CPUCFG_RST_CTRL_CPU_RESET __BIT(0)
@@ -1738,6 +1742,30 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_USB_CLK_PHY1_ENABLE __BIT(1)
#define AWIN_A31_USB_CLK_PHY0_ENABLE __BIT(0)
+#define AWIN_A31_AHB_RESET0_USBOHCI2_RST __BIT(31)
+#define AWIN_A31_AHB_RESET0_USBOHCI1_RST __BIT(30)
+#define AWIN_A31_AHB_RESET0_USBOHCI0_RST __BIT(29)
+#define AWIN_A31_AHB_RESET0_USBEHCI1_RST __BIT(27)
+#define AWIN_A31_AHB_RESET0_USBEHCI0_RST __BIT(26)
+#define AWIN_A31_AHB_RESET0_USBOTG_RST __BIT(24)
+#define AWIN_A31_AHB_RESET0_SPI3_RST __BIT(23)
+#define AWIN_A31_AHB_RESET0_SPI2_RST __BIT(22)
+#define AWIN_A31_AHB_RESET0_SPI1_RST __BIT(21)
+#define AWIN_A31_AHB_RESET0_SPI0_RST __BIT(20)
+#define AWIN_A31_AHB_RESET0_HSTMR_RST __BIT(19)
+#define AWIN_A31_AHB_RESET0_TS_RST __BIT(18)
+#define AWIN_A31_AHB_RESET0_GMAC_RST __BIT(17)
+#define AWIN_A31_AHB_RESET0_SDRAM_RST __BIT(14)
+#define AWIN_A31_AHB_RESET0_NAND0_RST __BIT(13)
+#define AWIN_A31_AHB_RESET0_NAND1_RST __BIT(12)
+#define AWIN_A31_AHB_RESET0_SD3_RST __BIT(11)
+#define AWIN_A31_AHB_RESET0_SD2_RST __BIT(10)
+#define AWIN_A31_AHB_RESET0_SD1_RST __BIT(9)
+#define AWIN_A31_AHB_RESET0_SD0_RST __BIT(8)
+#define AWIN_A31_AHB_RESET0_DMA_RST __BIT(6)
+#define AWIN_A31_AHB_RESET0_SS_RST __BIT(5)
+#define AWIN_A31_AHB_RESET0_MIPIDSI_RST __BIT(1)
+
#define AWIN_A31_WDOG1_IRQ_EN_REG 0x00A0
#define AWIN_A31_WDOG1_IRQ_STA_REG 0x00A4
#define AWIN_A31_WDOG1_CTRL_REG 0x00B0
Index: src/sys/arch/arm/allwinner/awin_usb.c
diff -u src/sys/arch/arm/allwinner/awin_usb.c:1.14 src/sys/arch/arm/allwinner/awin_usb.c:1.15
--- src/sys/arch/arm/allwinner/awin_usb.c:1.14 Fri Oct 10 07:36:11 2014
+++ src/sys/arch/arm/allwinner/awin_usb.c Sun Oct 12 13:07:45 2014
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.14 2014/10/10 07:36:11 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.15 2014/10/12 13:07:45 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -71,6 +71,7 @@ struct awinusb_softc {
bus_space_handle_t usbsc_usb0_phy_csr_bsh;
u_int usbsc_number;
struct awin_gpio_pindata usbsc_drv_pin;
+ struct awin_gpio_pindata usbsc_restrict_pin;
device_t usbsc_ohci_dev;
device_t usbsc_ehci_dev;
@@ -283,6 +284,8 @@ CFATTACH_DECL_NEW(awin_usb, sizeof(struc
static int awinusb_ports;
static const char awinusb_drvpin_names[2][8] = { "usb1drv", "usb2drv" };
+static const char awinusb_restrictpin_names[2][13] = { "usb1restrict", "usb2restrict" };
+
static const bus_size_t awinusb_dram_hpcr_regs[2] = {
AWIN_DRAM_HPCR_USB1_REG,
AWIN_DRAM_HPCR_USB2_REG,
@@ -331,6 +334,22 @@ static const uint32_t awinusb_usb_clk_se
AWIN_A31_USB_CLK_USBPHY2_ENABLE |
AWIN_A31_USB_CLK_PHY2_ENABLE,
};
+static const uint32_t awinusb_usb_ahb_reset_a31[2] = {
+#if NOHCI > 0
+ AWIN_A31_AHB_RESET0_USBOHCI0_RST |
+#endif
+#if NEHCI > 0
+ AWIN_A31_AHB_RESET0_USBEHCI0_RST |
+#endif
+ 0,
+#if NOHCI > 0
+ AWIN_A31_AHB_RESET0_USBOHCI1_RST |
+#endif
+#if NEHCI > 0
+ AWIN_A31_AHB_RESET0_USBEHCI1_RST |
+#endif
+ 0,
+};
int
awinusb_match(device_t parent, cfdata_t cf, void *aux)
@@ -374,19 +393,20 @@ awinusb_attach(device_t parent, device_t
aprint_normal("\n");
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
- /*
- * Access to the USB phy is off USB0 so make sure it's on.
- */
+ /* Enable USB PHY */
awin_reg_set_clear(usbsc->usbsc_bst, aio->aio_ccm_bsh,
- AWIN_AHB_GATING0_REG,
- awinusb_ahb_gating_a31[loc->loc_port], 0);
+ AWIN_USB_CLK_REG, awinusb_usb_clk_set_a31[loc->loc_port],
+ 0);
- /*
- * Enable the USB phy for this port.
- */
+ /* AHB gate enable */
awin_reg_set_clear(usbsc->usbsc_bst, aio->aio_ccm_bsh,
- AWIN_USB_CLK_REG, awinusb_usb_clk_set_a31[loc->loc_port],
+ AWIN_AHB_GATING0_REG,
+ AWIN_A31_AHB_GATING0_USB0 | awinusb_ahb_gating_a31[loc->loc_port],
0);
+
+ /* Soft reset */
+ awin_reg_set_clear(usbsc->usbsc_bst, aio->aio_ccm_bsh,
+ AWIN_A31_AHB_RESET0_REG, awinusb_usb_ahb_reset_a31[loc->loc_port], 0);
} else {
/*
* Access to the USB phy is off USB0 so make sure it's on.
@@ -432,6 +452,13 @@ awinusb_attach(device_t parent, device_t
aprint_error_dev(self, "no power gpio found\n");
}
+ if (awin_gpio_pin_reserve(awinusb_restrictpin_names[loc->loc_port],
+ &usbsc->usbsc_restrict_pin)) {
+ awin_gpio_pindata_write(&usbsc->usbsc_restrict_pin, 1);
+ } else {
+ aprint_error_dev(self, "no restrict gpio found\n");
+ }
+
/*
* Disable interrupts
*/
