Module Name: src
Committed By: jmcneill
Date: Sun Oct 12 23:57:59 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_intr.h awin_io.c awin_reg.h files.awin
Added Files:
src/sys/arch/arm/allwinner: awin_p2wi.c
Log Message:
add A31 P2WI (Push-Pull Two Wire Interface) driver
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/allwinner/awin_intr.h
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/allwinner/awin_io.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/allwinner/awin_p2wi.c
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/arm/allwinner/awin_reg.h
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/allwinner/files.awin
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_intr.h
diff -u src/sys/arch/arm/allwinner/awin_intr.h:1.6 src/sys/arch/arm/allwinner/awin_intr.h:1.7
--- src/sys/arch/arm/allwinner/awin_intr.h:1.6 Sun Oct 12 14:06:18 2014
+++ src/sys/arch/arm/allwinner/awin_intr.h Sun Oct 12 23:57:58 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_intr.h,v 1.6 2014/10/12 14:06:18 jmcneill Exp $ */
+/* $NetBSD: awin_intr.h,v 1.7 2014/10/12 23:57:58 jmcneill Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -148,6 +148,7 @@
#define AWIN_A31_IRQ_TWI2 40
#define AWIN_A31_IRQ_TWI3 41
#define AWIN_A31_IRQ_AC 61
+#define AWIN_A31_IRQ_P2WI 71
#define AWIN_A31_IRQ_DMA 82
#define AWIN_A31_IRQ_SDMMC0 92
#define AWIN_A31_IRQ_SDMMC1 93
Index: src/sys/arch/arm/allwinner/awin_io.c
diff -u src/sys/arch/arm/allwinner/awin_io.c:1.19 src/sys/arch/arm/allwinner/awin_io.c:1.20
--- src/sys/arch/arm/allwinner/awin_io.c:1.19 Sun Oct 12 17:20:46 2014
+++ src/sys/arch/arm/allwinner/awin_io.c Sun Oct 12 23:57:58 2014
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.19 2014/10/12 17:20:46 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.20 2014/10/12 23:57:58 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -132,6 +132,7 @@ static const struct awin_locators awin_l
{ "awiniic", OFFANDSIZE(TWI1), 1, AWIN_A31_IRQ_TWI1, A31 },
{ "awiniic", OFFANDSIZE(TWI2), 2, AWIN_A31_IRQ_TWI2, A31 },
{ "awiniic", OFFANDSIZE(TWI3), 3, AWIN_A31_IRQ_TWI3, A31 },
+ { "awinp2wi", OFFANDSIZE(A31_P2WI), NOPORT, AWIN_A31_IRQ_P2WI, A31 },
{ "spi", OFFANDSIZE(SPI0), 0, AWIN_IRQ_SPI0, AANY },
{ "spi", OFFANDSIZE(SPI1), 1, AWIN_IRQ_SPI1, AANY },
{ "spi", OFFANDSIZE(SPI2), 1, AWIN_IRQ_SPI2, AANY },
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.32 src/sys/arch/arm/allwinner/awin_reg.h:1.33
--- src/sys/arch/arm/allwinner/awin_reg.h:1.32 Sun Oct 12 17:19:12 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Sun Oct 12 23:57:58 2014
@@ -1703,6 +1703,7 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_PRCM_OFFSET 0x00301400 /* PRCM */
#define AWIN_A31_CPUCFG_OFFSET 0x00301C00
#define AWIN_A31_RTC_OFFSET 0x00300000 /* RTC */
+#define AWIN_A31_P2WI_OFFSET 0x00303400 /* P2WI */
#define AWIN_A31_PRCM_PWROFF_GATING_REG 0x100
#define AWIN_A31_PRCM_CPUX_PWR_CLAMP_REG 0x0140
@@ -1799,6 +1800,54 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_RTC_YY_MM_DD_YEAR __BITS(21,16)
+#define AWIN_A31_P2WI_CTRL_REG 0x0000
+#define AWIN_A31_P2WI_CCR_REG 0x0004
+#define AWIN_A31_P2WI_INTE_REG 0x0008
+#define AWIN_A31_P2WI_STAT_REG 0x000c
+#define AWIN_A31_P2WI_DADDR0_REG 0x0010
+#define AWIN_A31_P2WI_DADDR1_REG 0x0014
+#define AWIN_A31_P2WI_DLEN_REG 0x0018
+#define AWIN_A31_P2WI_DATA0_REG 0x001c
+#define AWIN_A31_P2WI_DATA1_REG 0x0020
+#define AWIN_A31_P2WI_LCR_REG 0x0024
+#define AWIN_A31_P2WI_PMCR_REG 0x0028
+
+#define AWIN_A31_P2WI_CTRL_START_TRANS __BIT(7)
+#define AWIN_A31_P2WI_CTRL_ABORT_TRANS __BIT(6)
+#define AWIN_A31_P2WI_CTRL_GLOBAL_INT_ENB __BIT(1)
+#define AWIN_A31_P2WI_CTRL_SOFT_RESET __BIT(0)
+
+#define AWIN_A31_P2WI_CCR_SDA_ODLY __BITS(10,8)
+#define AWIN_A31_P2WI_CCR_CLK_DIV __BITS(7,0)
+
+#define AWIN_A31_P2WI_INTE_LOAD_BSY_ENB __BIT(2)
+#define AWIN_A31_P2WI_INTE_TRANS_ERR_ENB __BIT(1)
+#define AWIN_A31_P2WI_INTE_TRANS_OVER_ENB __BIT(0)
+
+#define AWIN_A31_P2WI_STAT_TRANS_ERR_ID __BITS(15,8)
+#define AWIN_A31_P2WI_STAT_LOAD_BSY __BIT(2)
+#define AWIN_A31_P2WI_STAT_TRANS_ERR __BIT(1)
+#define AWIN_A31_P2WI_STAT_TRANS_OVER __BIT(0)
+#define AWIN_A31_P2WI_STAT_MASK \
+ (AWIN_A31_P2WI_STAT_LOAD_BSY | \
+ AWIN_A31_P2WI_STAT_TRANS_ERR | \
+ AWIN_A31_P2WI_STAT_TRANS_OVER)
+
+#define AWIN_A31_P2WI_DLEN_READ_WRITE_FLAG __BIT(4)
+#define AWIN_A31_P2WI_DLEN_ACCESS_LENGTH __BITS(2,0)
+
+#define AWIN_A31_P2WI_LCR_SCL_STATE __BIT(5)
+#define AWIN_A31_P2WI_LCR_SDA_STATE __BIT(4)
+#define AWIN_A31_P2WI_LCR_SCL_CTL __BIT(3)
+#define AWIN_A31_P2WI_LCR_SCL_CTL_EN __BIT(2)
+#define AWIN_A31_P2WI_LCR_SDA_CTL __BIT(1)
+#define AWIN_A31_P2WI_LCR_SDA_CTL_EN __BIT(0)
+
+#define AWIN_A31_P2WI_PMCR_PMU_INIT_SEND __BIT(31)
+#define AWIN_A31_P2WI_PMCR_PMU_INIT_DATA __BITS(23,16)
+#define AWIN_A31_P2WI_PMCR_PMU_MODE_CTRL_REG_ADDR __BITS(15,8)
+#define AWIN_A31_P2WI_PMCR_PMU_DEVICE_ADDR __BITS(7,0)
+
#define AWIN_A31_PIO_PB_TWI3_FUNC 2
#define AWIN_A31_PIO_PB_TWI3_PINS 0x00000060 /* PB pins 6-5 */
Index: src/sys/arch/arm/allwinner/files.awin
diff -u src/sys/arch/arm/allwinner/files.awin:1.15 src/sys/arch/arm/allwinner/files.awin:1.16
--- src/sys/arch/arm/allwinner/files.awin:1.15 Fri Oct 10 17:48:30 2014
+++ src/sys/arch/arm/allwinner/files.awin Sun Oct 12 23:57:58 2014
@@ -1,4 +1,4 @@
-# $NetBSD: files.awin,v 1.15 2014/10/10 17:48:30 jmcneill Exp $
+# $NetBSD: files.awin,v 1.16 2014/10/12 23:57:58 jmcneill Exp $
#
# Configuration info for Allwinner ARM Peripherals
#
@@ -73,6 +73,11 @@ device awiniic : i2cbus, i2cexec, mvi2c
attach awiniic at awinio with awin_twi
file arch/arm/allwinner/awin_twi.c awin_twi
+# A31 P2WI
+device awinp2wi : i2cbus, i2cexec
+attach awinp2wi at awinio with awin_p2wi
+file arch/arm/allwinner/awin_p2wi.c awin_p2wi
+
# A10/A20 NAND controller
device awinnand : nandbus
attach awinnand at awinio with awin_nand
Added files:
Index: src/sys/arch/arm/allwinner/awin_p2wi.c
diff -u /dev/null src/sys/arch/arm/allwinner/awin_p2wi.c:1.1
--- /dev/null Sun Oct 12 23:57:59 2014
+++ src/sys/arch/arm/allwinner/awin_p2wi.c Sun Oct 12 23:57:58 2014
@@ -0,0 +1,251 @@
+/* $NetBSD: awin_p2wi.c,v 1.1 2014/10/12 23:57:58 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: awin_p2wi.c,v 1.1 2014/10/12 23:57:58 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+
+#include <arm/allwinner/awin_reg.h>
+#include <arm/allwinner/awin_var.h>
+
+#include <dev/i2c/i2cvar.h>
+
+struct awin_p2wi_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ struct i2c_controller sc_ic;
+ kmutex_t sc_lock;
+ kcondvar_t sc_cv;
+ device_t sc_i2cdev;
+ void *sc_ih;
+ uint32_t sc_stat;
+};
+
+#define P2WI_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define P2WI_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+static int awin_p2wi_acquire_bus(void *, int);
+static void awin_p2wi_release_bus(void *, int);
+static int awin_p2wi_exec(void *, i2c_op_t, i2c_addr_t, const void *,
+ size_t, void *, size_t, int);
+
+static int awin_p2wi_intr(void *);
+
+static int awin_p2wi_match(device_t, cfdata_t, void *);
+static void awin_p2wi_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(awin_p2wi, sizeof(struct awin_p2wi_softc),
+ awin_p2wi_match, awin_p2wi_attach, NULL, NULL);
+
+static int
+awin_p2wi_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct awinio_attach_args * const aio = aux;
+ const struct awin_locators * const loc = &aio->aio_loc;
+
+ if (strcmp(cf->cf_name, loc->loc_name))
+ return 0;
+
+ return 1;
+}
+
+static void
+awin_p2wi_attach(device_t parent, device_t self, void *aux)
+{
+ struct awin_p2wi_softc *sc = device_private(self);
+ struct awinio_attach_args * const aio = aux;
+ const struct awin_locators * const loc = &aio->aio_loc;
+ struct i2cbus_attach_args iba;
+
+ sc->sc_dev = self;
+ sc->sc_bst = aio->aio_core_bst;
+ mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED);
+ cv_init(&sc->sc_cv, "awinp2wi");
+ bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+
+ aprint_naive("\n");
+ aprint_normal(": P2WI\n");
+
+ sc->sc_ih = intr_establish(loc->loc_intr, IPL_SCHED, IST_LEVEL,
+ awin_p2wi_intr, sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt %d\n",
+ loc->loc_intr);
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
+
+ /* Enable interrupts */
+ P2WI_WRITE(sc, AWIN_A31_P2WI_INTE_REG,
+ AWIN_A31_P2WI_INTE_LOAD_BSY_ENB |
+ AWIN_A31_P2WI_INTE_TRANS_ERR_ENB |
+ AWIN_A31_P2WI_INTE_TRANS_OVER_ENB);
+ P2WI_WRITE(sc, AWIN_A31_P2WI_CTRL_REG,
+ AWIN_A31_P2WI_CTRL_GLOBAL_INT_ENB);
+
+ sc->sc_ic.ic_cookie = sc;
+ sc->sc_ic.ic_acquire_bus = awin_p2wi_acquire_bus;
+ sc->sc_ic.ic_release_bus = awin_p2wi_release_bus;
+ sc->sc_ic.ic_exec = awin_p2wi_exec;
+
+ memset(&iba, 0, sizeof(iba));
+ iba.iba_tag = &sc->sc_ic;
+ sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print);
+}
+
+static int
+awin_p2wi_intr(void *priv)
+{
+ struct awin_p2wi_softc *sc = priv;
+ uint32_t stat;
+
+ stat = P2WI_READ(sc, AWIN_A31_P2WI_STAT_REG);
+ if ((stat & AWIN_A31_P2WI_STAT_MASK) == 0)
+ return 0;
+
+ P2WI_WRITE(sc, AWIN_A31_P2WI_STAT_REG, stat & AWIN_A31_P2WI_STAT_MASK);
+
+ mutex_enter(&sc->sc_lock);
+ sc->sc_stat |= stat;
+ cv_broadcast(&sc->sc_cv);
+ mutex_exit(&sc->sc_lock);
+
+ return 1;
+}
+
+static int
+awin_p2wi_acquire_bus(void *priv, int flags)
+{
+ struct awin_p2wi_softc *sc = priv;
+
+ if (flags & I2C_F_POLL) {
+ if (!mutex_tryenter(&sc->sc_lock))
+ return EBUSY;
+ } else {
+ mutex_enter(&sc->sc_lock);
+ }
+
+ return 0;
+}
+
+static void
+awin_p2wi_release_bus(void *priv, int flags)
+{
+ struct awin_p2wi_softc *sc = priv;
+
+ mutex_exit(&sc->sc_lock);
+}
+
+static int
+awin_p2wi_exec(void *priv, i2c_op_t op, i2c_addr_t addr,
+ const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
+{
+ struct awin_p2wi_softc *sc = priv;
+ uint32_t dlen, ctrl;
+ int error, retry;
+
+ KASSERT(mutex_owned(&sc->sc_lock));
+
+ if (cmdlen != 1 || len != 1)
+ return EINVAL;
+
+ /* Data byte register */
+ P2WI_WRITE(sc, AWIN_A31_P2WI_DADDR0_REG, *(const uint8_t *)cmdbuf);
+
+ if (I2C_OP_WRITE_P(op)) {
+ /* Write data byte */
+ P2WI_WRITE(sc, AWIN_A31_P2WI_DATA0_REG, *(uint8_t *)buf);
+ }
+
+ /* Program data length register; if reading, set read/write bit */
+ dlen = __SHIFTIN(len - 1, AWIN_A31_P2WI_DLEN_ACCESS_LENGTH);
+ if (I2C_OP_READ_P(op)) {
+ dlen |= AWIN_A31_P2WI_DLEN_READ_WRITE_FLAG;
+ }
+ P2WI_WRITE(sc, AWIN_A31_P2WI_DLEN_REG, dlen);
+
+ /* Make sure the controller is idle */
+ ctrl = P2WI_READ(sc, AWIN_A31_P2WI_CTRL_REG);
+ if (ctrl & AWIN_A31_P2WI_CTRL_START_TRANS) {
+ device_printf(sc->sc_dev, "device is busy\n");
+ return EBUSY;
+ }
+
+ /* Start the transfer */
+ P2WI_WRITE(sc, AWIN_A31_P2WI_CTRL_REG,
+ ctrl | AWIN_A31_P2WI_CTRL_START_TRANS);
+
+ /* Wait up to 5 seconds for an interrupt */
+ sc->sc_stat = 0;
+ for (retry = 5; retry > 0; retry--) {
+ error = cv_timedwait(&sc->sc_cv, &sc->sc_lock, hz);
+ if (error && error != EWOULDBLOCK) {
+ break;
+ }
+ if (sc->sc_stat & AWIN_A31_P2WI_STAT_MASK) {
+ break;
+ }
+ }
+
+ if (error) {
+ /* Abort transaction */
+ device_printf(sc->sc_dev, "transfer timeout, error = %d\n",
+ error);
+ P2WI_WRITE(sc, AWIN_A31_P2WI_CTRL_REG,
+ AWIN_A31_P2WI_CTRL_ABORT_TRANS);
+ return error;
+ }
+
+ if (sc->sc_stat & AWIN_A31_P2WI_STAT_LOAD_BSY) {
+ device_printf(sc->sc_dev, "transfer busy\n");
+ return EBUSY;
+ }
+ if (sc->sc_stat & AWIN_A31_P2WI_STAT_TRANS_ERR) {
+ device_printf(sc->sc_dev, "transfer error, id 0x%02llx\n",
+ __SHIFTOUT(sc->sc_stat, AWIN_A31_P2WI_STAT_TRANS_ERR_ID));
+ return EIO;
+ }
+
+ if (I2C_OP_READ_P(op)) {
+ *(uint8_t *)buf = P2WI_READ(sc, AWIN_A31_P2WI_DATA0_REG) & 0xff;
+ }
+
+ return 0;
+}
