Module Name: src
Committed By: jmcneill
Date: Sun Oct 12 17:19:12 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h
Log Message:
more A31 regs
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.31 src/sys/arch/arm/allwinner/awin_reg.h:1.32
--- src/sys/arch/arm/allwinner/awin_reg.h:1.31 Sun Oct 12 14:06:18 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Sun Oct 12 17:19:12 2014
@@ -1702,6 +1702,7 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_USB3_OFFSET 0x0001c000 /* OHCI2 */
#define AWIN_A31_PRCM_OFFSET 0x00301400 /* PRCM */
#define AWIN_A31_CPUCFG_OFFSET 0x00301C00
+#define AWIN_A31_RTC_OFFSET 0x00300000 /* RTC */
#define AWIN_A31_PRCM_PWROFF_GATING_REG 0x100
#define AWIN_A31_PRCM_CPUX_PWR_CLAMP_REG 0x0140
@@ -1721,10 +1722,17 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_AHB_RESET0_REG 0x02C0
#define AWIN_A31_AHB_RESET1_REG 0x02C4
#define AWIN_A31_AHB_RESET2_REG 0x02C8
+#define AWIN_A31_APB1_RESET_REG 0x02D0
#define AWIN_A31_CPUCFG_RST_CTRL_CORE_RESET __BIT(1)
#define AWIN_A31_CPUCFG_RST_CTRL_CPU_RESET __BIT(0)
+#define AWIN_A31_PLL2_CFG_LOCK __BIT(28)
+#define AWIN_A31_PLL2_CFG_PLL_SDM_EN __BIT(24)
+#define AWIN_A31_PLL2_CFG_POSTDIV_P __BITS(19,16)
+#define AWIN_A31_PLL2_CFG_FACTOR_N __BITS(14,8)
+#define AWIN_A31_PLL2_CFG_PREVDIV_M __BITS(4,0)
+
#define AWIN_A31_AHB_GATING0_USB_OHCI2 __BIT(31)
#define AWIN_A31_AHB_GATING0_USB_OHCI1 __BIT(30)
#define AWIN_A31_AHB_GATING0_USB_OHCI0 __BIT(29)
@@ -1766,6 +1774,11 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_AHB_RESET0_SS_RST __BIT(5)
#define AWIN_A31_AHB_RESET0_MIPIDSI_RST __BIT(1)
+#define AWIN_A31_APB1_RESET_DAUDIO1_RST __BIT(13)
+#define AWIN_A31_APB1_RESET_DAUDIO0_RST __BIT(12)
+#define AWIN_A31_APB1_RESET_DIGITAL_MIC_RST __BIT(4)
+#define AWIN_A31_APB1_RESET_CODEC_RST __BIT(0)
+
#define AWIN_A31_WDOG1_IRQ_EN_REG 0x00A0
#define AWIN_A31_WDOG1_IRQ_STA_REG 0x00A4
#define AWIN_A31_WDOG1_CTRL_REG 0x00B0
@@ -1780,6 +1793,12 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_MMC_FIFO 0x0200
+#define AWIN_A31_LOSC_CTRL_REG 0x0000
+#define AWIN_A31_RTC_YY_MM_DD_REG 0x0010
+#define AWIN_A31_RTC_HH_MM_SS_REG 0x0014
+
+#define AWIN_A31_RTC_YY_MM_DD_YEAR __BITS(21,16)
+
#define AWIN_A31_PIO_PB_TWI3_FUNC 2
#define AWIN_A31_PIO_PB_TWI3_PINS 0x00000060 /* PB pins 6-5 */
