Module Name: src
Committed By: hsuenaga
Date: Wed Apr 15 10:40:36 UTC 2015
Modified Files:
src/sys/arch/arm/marvell: armadaxp.c armadaxpreg.h
Added Files:
src/sys/arch/arm/marvell: armadaxpvar.h
Log Message:
implement L2 cache maintenance operations of ARMADA XP.
the L2 cahce maintenance operations are defined on SoC internal registers.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/marvell/armadaxp.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/marvell/armadaxpreg.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/marvell/armadaxpvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/armadaxp.c
diff -u src/sys/arch/arm/marvell/armadaxp.c:1.8 src/sys/arch/arm/marvell/armadaxp.c:1.9
--- src/sys/arch/arm/marvell/armadaxp.c:1.8 Sat Apr 5 22:41:50 2014
+++ src/sys/arch/arm/marvell/armadaxp.c Wed Apr 15 10:40:36 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.8 2014/04/05 22:41:50 matt Exp $ */
+/* $NetBSD: armadaxp.c,v 1.9 2015/04/15 10:40:36 hsuenaga Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.8 2014/04/05 22:41:50 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.9 2015/04/15 10:40:36 hsuenaga Exp $");
#define _INTR_PRIVATE
@@ -58,6 +58,7 @@ __KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v
#include <arm/marvell/mvsocreg.h>
#include <arm/marvell/mvsocvar.h>
#include <arm/marvell/armadaxpreg.h>
+#include <arm/marvell/armadaxpvar.h>
#include <dev/marvell/marvellreg.h>
@@ -99,8 +100,6 @@ static void armadaxp_pic_set_priority(st
static int armadaxp_find_pending_irqs(void);
static void armadaxp_pic_block_irq(struct pic_softc *, size_t);
-void armadaxp_io_coherency_init(void);
-int armadaxp_l2_init(bus_addr_t);
struct vco_freq_ratio {
uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
@@ -477,6 +476,61 @@ armadaxp_l2_init(bus_addr_t pbase)
}
void
+armadaxp_sdcache_inv_all(void)
+{
+ L2_WRITE(ARMADAXP_L2_INV_WAY, L2_ALL_WAYS);
+}
+
+void
+armadaxp_sdcache_wb_all(void)
+{
+ L2_WRITE(ARMADAXP_L2_WB_WAY, L2_ALL_WAYS);
+ __asm__ __volatile__("dsb");
+}
+
+void
+armadaxp_sdcache_wbinv_all(void)
+{
+ L2_WRITE(ARMADAXP_L2_WBINV_WAY, L2_ALL_WAYS);
+ __asm__ __volatile__("dsb");
+}
+
+void
+armadaxp_sdcache_inv_range(vaddr_t va, paddr_t pa, psize_t sz)
+{
+ paddr_t pa_base, pa_end;
+
+ pa_base = pa & ~0x1f;
+ pa_end = (pa_base + sz) & ~0x1f;
+ L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
+ L2_WRITE(ARMADAXP_L2_INV_RANGE, pa_end);
+}
+
+void
+armadaxp_sdcache_wb_range(vaddr_t va, paddr_t pa, psize_t sz)
+{
+ paddr_t pa_base, pa_end;
+
+ pa_base = pa & ~0x1f;
+ pa_end = (pa_base + sz) & ~0x1f;
+ L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
+ L2_WRITE(ARMADAXP_L2_WB_RANGE, pa_end);
+ __asm__ __volatile__("dsb");
+}
+
+void
+armadaxp_sdcache_wbinv_range(vaddr_t va, paddr_t pa, psize_t sz)
+{
+ paddr_t pa_base, pa_end;
+
+ pa_base = pa & ~0x1f;
+ pa_end = (pa_base + sz) & ~0x1f;
+ L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
+ L2_WRITE(ARMADAXP_L2_WBINV_RANGE, pa_end);
+ __asm__ __volatile__("dsb");
+}
+
+void
armadaxp_io_coherency_init(void)
{
uint32_t reg;
Index: src/sys/arch/arm/marvell/armadaxpreg.h
diff -u src/sys/arch/arm/marvell/armadaxpreg.h:1.2 src/sys/arch/arm/marvell/armadaxpreg.h:1.3
--- src/sys/arch/arm/marvell/armadaxpreg.h:1.2 Mon Dec 23 03:19:43 2013
+++ src/sys/arch/arm/marvell/armadaxpreg.h Wed Apr 15 10:40:36 2015
@@ -222,7 +222,23 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc)
#define ARMADAXP_L2_INT_CAUSE 0x220
#define ARMADAXP_L2_CFU 0x228
-#define ARMADAXP_L2_INV_WAY 0x778
+#define ARMADAXP_L2_SYNC 0x700
+#define ARMADAXP_L2_STATUS 0x704
+/* Cache maintance operations */
+#define ARMADAXP_L2_RANGE_BASE 0x720
+#define ARMADAXP_L2_INV_PHYS 0x770
+#define ARMADAXP_L2_INV_RANGE 0x774
+#define ARMADAXP_L2_INV_IDXWAY 0x778
+#define ARMADAXP_L2_INV_WAY 0x77c
+#define ARMADAXP_L2_BLOCK 0x78c
+#define ARMADAXP_L2_WB_PHYS 0x7b0
+#define ARMADAXP_L2_WB_RANGE 0x7b4
+#define ARMADAXP_L2_WB_IDXWAY 0x7b8
+#define ARMADAXP_L2_WB_WAY 0x7bc
+#define ARMADAXP_L2_WBINV_PHYS 0x7f0
+#define ARMADAXP_L2_WBINV_RANGE 0x7f4
+#define ARMADAXP_L2_WBINV_IDXWAY 0x7f8
+#define ARMADAXP_L2_WBINV_WAY 0x7fc
#define L2_ENABLE (1 << 0)
#define L2_WBWT_MODE_MASK (3 << 0)
#define L2_REP_STRAT_MASK (3 << 27)
Added files:
Index: src/sys/arch/arm/marvell/armadaxpvar.h
diff -u /dev/null src/sys/arch/arm/marvell/armadaxpvar.h:1.1
--- /dev/null Wed Apr 15 10:40:36 2015
+++ src/sys/arch/arm/marvell/armadaxpvar.h Wed Apr 15 10:40:36 2015
@@ -0,0 +1,44 @@
+/* $NetBSD: armadaxpvar.h,v 1.1 2015/04/15 10:40:36 hsuenaga Exp $ */
+/*
+ * Copyright (c) 2015 SUENAGA Hiroki
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ARMDAXPVAR_H_
+#define _ARMDAXPVAR_H_
+#include <machine/bus_defs.h>
+
+/* device initalization */
+extern void armadaxp_io_coherency_init(void);
+extern int armadaxp_l2_init(bus_addr_t);
+
+/* l2cache maintanance */
+extern void armadaxp_sdcache_inv_all(void);
+extern void armadaxp_sdcache_wb_all(void);
+extern void armadaxp_sdcache_wbinv_all(void);
+extern void armadaxp_sdcache_inv_range(vaddr_t, paddr_t, psize_t);
+extern void armadaxp_sdcache_wb_range(vaddr_t, paddr_t, psize_t);
+extern void armadaxp_sdcache_wbinv_range(vaddr_t, paddr_t, psize_t);
+
+#endif /* _ARMDAXPVAR_H_ */
+
