Module Name: src
Committed By: hsuenaga
Date: Wed Jun 3 02:53:19 UTC 2015
Modified Files:
src/sys/arch/arm/marvell: armadaxp.c armadaxpreg.h armadaxpvar.h
Log Message:
add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.
add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/marvell/armadaxp.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/marvell/armadaxpreg.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/marvell/armadaxpvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/armadaxp.c
diff -u src/sys/arch/arm/marvell/armadaxp.c:1.14 src/sys/arch/arm/marvell/armadaxp.c:1.15
--- src/sys/arch/arm/marvell/armadaxp.c:1.14 Tue May 19 09:20:19 2015
+++ src/sys/arch/arm/marvell/armadaxp.c Wed Jun 3 02:53:19 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.14 2015/05/19 09:20:19 hsuenaga Exp $ */
+/* $NetBSD: armadaxp.c,v 1.15 2015/06/03 02:53:19 hsuenaga Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.14 2015/05/19 09:20:19 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.15 2015/06/03 02:53:19 hsuenaga Exp $");
#define _INTR_PRIVATE
@@ -97,10 +97,20 @@ static void armadaxp_pic_unblock_irqs(st
static void armadaxp_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
static void armadaxp_pic_establish_irq(struct pic_softc *, struct intrsource *);
static void armadaxp_pic_set_priority(struct pic_softc *, int);
+static void armadaxp_pic_source_name(struct pic_softc *, int, char*, size_t);
static int armadaxp_find_pending_irqs(void);
static void armadaxp_pic_block_irq(struct pic_softc *, size_t);
+/* handle error cause */
+static void armadaxp_err_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
+static void armadaxp_err_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
+static void armadaxp_err_pic_establish_irq(struct pic_softc *,
+ struct intrsource *);
+static void armadaxp_err_pic_source_name(struct pic_softc *,
+ int, char*, size_t);
+static int armadaxp_err_pic_pending_irqs(struct pic_softc *);
+
struct vco_freq_ratio {
uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */
@@ -108,6 +118,303 @@ struct vco_freq_ratio {
uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */
};
+/*
+ * Interrupt names for ARMADA XP
+ */
+static const char * const armadaxp_pic_source_names[] = {
+ /* Main Interrupt Cause Per-CPU (IRQ 0-29) */
+ "InDBLowSum", "InDBHighSum", "OutDBSum", "CFU_LocalSum",
+ "SoC_ErrorSum", "LTimer0", "LTimer1", "LWDT", "GbE0_TH_RxTx",
+ "GbE0_RxTx", "GbE1_RxTxTh", "GbE1_RxTx", "GbE2_RxTxTh", "GbE2_RxTx",
+ "GbE3_RxTxTh", "GbE3_RxTx", "GPIO0_7", "GPIO8_15", "GPIO16_23",
+ "GPIO24_31", "GPIO32_39", "GPIO40_47", "GPIO48_55", "GPIO56_63",
+ "GPIO64_66", "SCNT", "PCNT", "Reserved27", "VCNT", "Reserved29",
+ /* Main Interrupt Cause Global-Shared (IRQ 30-115) */
+ "SPI0", "I2C0", "I2C1", "IDMA0", "IDMA1", "IDMA2", "IDMA3", "GTimer0",
+ "GTimer1", "GTimer2", "GTimer3", "UART0", "UART1", "UART2", "UART3",
+ "USB0", "USB1", "USB2", "CESA0", "CESA1", "RTC", "XOR0_Ch0",
+ "XOR0_Ch1", "BM", "SDIO", "SATA0", "TDM", "SATA1", "PEX0_0", "PEX0_1",
+ "PEX0_2", "PEX0_3", "PEX1_0", "PEX1_1", "PEX1_2", "PEX1_3",
+ "GbE0_Sum", "GbE0_Rx", "GbE0_Tx", "GbE0_Misc", "GbE1_Sum", "GbE1_Rx",
+ "GbE1_Tx", "GbE1_Misc", "GbE2_Sum", "GbE2_Rx", "GbE2_Tx", "GbE2_Misc",
+ "GbE3_Sum", "GbE3_Rx", "GbE3_Tx", "GbE3_Misc", "GPIO0_7", "GPIO8_15",
+ "GPIO16_23", "GPIO24_31", "Reserved86", "GPIO32_39", "GPIO40_47",
+ "GPIO48_55", "GPIO56_63", "GPIO64_66", "SPI1", "WDT", "XOR1_Ch2",
+ "XOR1_Ch3", "SharedDB1Sum", "SharedDB2Sum", "SharedDB3Sum", "PEX2_0",
+ "Reserved100", "Reserved101", "Reserved102", "PEX3_0", "Reserved104",
+ "Reserved105", "Reserved106", "PMU", "DRAM", "GbE0_Wakeup",
+ "GbE1_Wakeup", "GbE2_Wakeup", "GbE3_Wakeup", "NAND", "Reserved114",
+ "Reserved115"
+};
+static const char * const armadaxp_err_pic_source_names[] = {
+ /*
+ * IRQ 120-151 (bit 0-31 in SoC Error Interrupt Cause register)
+ * connected to SoC_ErrorSum in Main Interrupt Cause
+ */
+ "ERR_CESA0", "ERR_DevBus", "ERR_IDMA", "ERR_XOR1",
+ "ERR_PEX0", "ERR_PEX1", "ERR_GbE", "ERR_CESA1",
+ "ERR_USB", "ERR_DRAM", "ERR_XOR0", "ERR_Reserved11",
+ "ERR_BM", "ERR_CIB", "ERR_Reserved14", "ERR_PEX2",
+ "ERR_PEX3", "ERR_SATA0", "ERR_SATA1", "ERR_Reserved19",
+ "ERR_TDM", "ERR_NAND", "ERR_Reserved22",
+ "ERR_Reserved23", "ERR_Reserved24", "ERR_Reserved25",
+ "ERR_Reserved26", "ERR_Reserved27", "ERR_Reserved28",
+ "ERR_Reserved29", "ERR_Reserved30", "ERR_Reserved31",
+};
+
+/*
+ * Mbus Target and Attribute bindings for ARMADA XP
+ */
+static struct mbus_description {
+ uint8_t target;
+ uint8_t attr;
+ const char *string;
+} mbus_desc[] = {
+ /* DDR */
+ { ARMADAXP_UNITID_DDR, ARMADAXP_ATTR_DDR_CS0,
+ "DDR(M_CS[0])" },
+ { ARMADAXP_UNITID_DDR, ARMADAXP_ATTR_DDR_CS1,
+ "DDR(M_CS[1])" },
+ { ARMADAXP_UNITID_DDR, ARMADAXP_ATTR_DDR_CS2,
+ "DDR(M_CS[2])" },
+ { ARMADAXP_UNITID_DDR, ARMADAXP_ATTR_DDR_CS3,
+ "DDR(M_CS[3])" },
+
+ /* DEVBUS */
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS0,
+ "DEVBUS(SPI0 CS0)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS1,
+ "DEVBUS(SPI0 CS1)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS2,
+ "DEVBUS(SPI0 CS2)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS3,
+ "DEVBUS(SPI0 CS3)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS4,
+ "DEVBUS(SPI0 CS4)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS5,
+ "DEVBUS(SPI0 CS5)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS6,
+ "DEVBUS(SPI0 CS6)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS7,
+ "DEVBUS(SPI0 CS7)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS0,
+ "DEVBUS(SPI1 CS0)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS1,
+ "DEVBUS(SPI1 CS1)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS2,
+ "DEVBUS(SPI1 CS2)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS3,
+ "DEVBUS(SPI1 CS3)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS4,
+ "DEVBUS(SPI1 CS4)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS5,
+ "DEVBUS(SPI1 CS5)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS6,
+ "DEVBUS(SPI1 CS6)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS7,
+ "DEVBUS(SPI1 CS7)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS0,
+ "DEVBUS(DevCS[0])" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS1,
+ "DEVBUS(DevCS[1])" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS2,
+ "DEVBUS(DevCS[2])" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS3,
+ "DEVBUS(DevCS[3])" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_BOOT_CS,
+ "DEVBUS(BootCS)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_BOOT_ROM,
+ "DEVBUS(BootROM)" },
+
+ /* GbE */
+ { ARMADAXP_UNITID_GBE0, ARMADAXP_ATTR_GBE_RESERVED,
+ "GBE0 GBE1" },
+ { ARMADAXP_UNITID_GBE2, ARMADAXP_ATTR_GBE_RESERVED,
+ "GBE2 GBE3" },
+
+ /* PEX(PCIe) */
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx0_MEM,
+ "PEX0(Lane0, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx1_MEM,
+ "PEX0(Lane1, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx2_MEM,
+ "PEX0(Lane2, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx3_MEM,
+ "PEX0(Lane3, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEX2_MEM,
+ "PEX2(Lane0, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx0_MEM,
+ "PEX1(Lane0, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx1_MEM,
+ "PEX1(Lane1, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx2_MEM,
+ "PEX1(Lane2, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx3_MEM,
+ "PEX1(Lane3, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEX2_MEM,
+ "PEX3(Lane0, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx0_IO,
+ "PEX0(Lane0, I/O)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx1_IO,
+ "PEX0(Lane1, I/O)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx2_IO,
+ "PEX0(Lane2, I/O)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx3_IO,
+ "PEX0(Lane3, I/O)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEX2_IO,
+ "PEX2(Lane0, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx0_IO,
+ "PEX1(Lane0, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx1_IO,
+ "PEX1(Lane1, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx2_IO,
+ "PEX1(Lane2, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx3_IO,
+ "PEX1(Lane3, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEX2_IO,
+ "PEX3(Lane0, I/O)" },
+
+ /* CRYPT */
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_NOSWAP,
+ "CESA0(No swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_SWAP_BYTE,
+ "CESA0(Byte swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_SWAP_BYTE_WORD,
+ "CESA0(Byte and word swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_SWAP_WORD,
+ "CESA0(Word swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT1_NOSWAP,
+ "CESA1(No swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT1_SWAP_BYTE,
+ "CESA1(Byte swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT1_SWAP_BYTE_WORD,
+ "CESA1(Byte and word swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT1_SWAP_WORD,
+ "CESA1(Word swap)" },
+
+ /* BM */
+ { ARMADAXP_UNITID_BM, ARMADAXP_ATTR_BM_RESERVED,
+ "BM" },
+
+ /* NAND */
+ { ARMADAXP_UNITID_NAND, ARMADAXP_ATTR_NAND_RESERVED,
+ "NAND" },
+};
+
+/*
+ * Default Mbus addrss decoding table for ARMADA XP
+ * this table may changed by device drivers.
+ *
+ * NOTE: some version of u-boot is broken. it writes old decoding table.
+ * probably, it's designed for Kirkwood SoC or older. we need to restore
+ * ARMADA XP's parameter set.
+ */
+static struct mbus_table_def {
+ int window; /* index of address decoding window registers */
+ uint32_t base; /* base address of the window */
+ uint32_t size; /* size of the window */
+ uint8_t target; /* target unit of the window */
+ uint8_t attr; /* target attribute of the window */
+} mbus_table[] = {
+ /*
+ * based on 'default address mapping' described in Marvell's document
+ * 'ARMADA XP Functional Specifications.'
+ *
+ * some windows are modified to get compatibility with old codes.
+ */
+ {
+ /* PCIe 0 lane0 MEM */
+ /* MODIFIED (moved to MARVELL_PEXMEM_PBASE) */
+ 0, 0xe0000000, 0x01000000,
+ ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx0_MEM
+ },
+ {
+ /* PCIe 0 lane1 MEM */
+ 1, 0x88000000, 0x08000000,
+ ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx1_MEM
+ },
+ {
+ /* PCIe 0 lane2 MEM */
+ 2, 0x90000000, 0x08000000,
+ ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx2_MEM
+ },
+ {
+ /* PCIe 0 lane3 MEM */
+ 3, 0x98000000, 0x08000000,
+ ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx3_MEM
+ },
+ {
+ /* PCIe 1 lane0 MEM */
+ 4, 0xa0000000, 0x08000000,
+ ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx0_MEM
+ },
+ { 5, 0, 0, 0, 0 /* disabled */ },
+ { 6, 0, 0, 0, 0 /* disabled */ },
+ { 7, 0, 0, 0, 0 /* disabled */ },
+ {
+ /* Security Accelerator SRAM, Engine 0, no data swap */
+ 8, 0xc8010000, 0x00010000,
+ ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_NOSWAP,
+ },
+ {
+ /* Device bus, BOOT_CS */
+ 9, 0xd8000000, 0x08000000,
+ ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_BOOT_CS,
+ },
+ {
+ /* Device bus, DEV_CS[0] */
+ /* MODIFIED (moved, conflict to MARVELL_PEXMEM_PBASE here.) */
+ 10, 0x80000000, 0x08000000,
+ ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS0
+ },
+ {
+ /* Device bus, DEV_CS[1] */
+ 11, 0xe8000000, 0x08000000,
+ ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS1
+ },
+ {
+ /* Device bus, DEV_CS[2] */
+ /* MODIFIED: (disabled, conflict to MARVELL_PEXIO_PBASE) */
+ 12, 0xf0000000, 0x00000000,
+ ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS2
+ },
+ {
+ /* Device bus, BOOT_ROM */
+ 13, 0xf8000000, 0x08000000,
+ ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_BOOT_ROM
+ },
+ {
+ /* Device bus, SPI0_CS[0] */
+ 14, 0xd4000000, 0x04000000,
+ ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS0
+ },
+ {
+ /* Security Accelerator SRAM, Engine 1, no data swap */
+ /* MODIFIED (added, 0xd0300000-0xd030ffff) */
+ 15, 0xd0300000, 0x00010000,
+ ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT1_NOSWAP
+ },
+ {
+ /* PCIe 0 lane 0 I/O */
+ /* MODIFIED (added, MARVELL_PEXIO_PBASE) */
+ 16, 0xf2000000, 0x00100000,
+ ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx0_IO
+ },
+ { 17, 0xd0320000, 0, 0, 0 /* disabled */ },
+ {
+ /* Buffer Manamgement unit */
+ 18, 0xd3800000, 0x00800000,
+ ARMADAXP_UNITID_BM, ARMADAXP_ATTR_BM_RESERVED
+ },
+ {
+ /* DDR */
+ /* MODIFIED (up to 2GB memory space) */
+ 19, 0x00000000, 0x80000000,
+ ARMADAXP_UNITID_DDR, ARMADAXP_ATTR_DDR_CS0
+ },
+
+};
+
static struct vco_freq_ratio freq_conf_table[] = {
/*00*/ { 1, 1, 4, 2 },
/*01*/ { 1, 2, 2, 2 },
@@ -149,6 +456,7 @@ static struct pic_ops armadaxp_picops =
.pic_block_irqs = armadaxp_pic_block_irqs,
.pic_establish_irq = armadaxp_pic_establish_irq,
.pic_set_priority = armadaxp_pic_set_priority,
+ .pic_source_name = armadaxp_pic_source_name,
};
static struct pic_softc armadaxp_pic = {
@@ -156,6 +464,19 @@ static struct pic_softc armadaxp_pic = {
.pic_name = "armadaxp",
};
+static struct pic_ops armadaxp_err_picops = {
+ .pic_unblock_irqs = armadaxp_err_pic_unblock_irqs,
+ .pic_block_irqs = armadaxp_err_pic_block_irqs,
+ .pic_establish_irq = armadaxp_err_pic_establish_irq,
+ .pic_find_pending_irqs = armadaxp_err_pic_pending_irqs,
+ .pic_source_name = armadaxp_err_pic_source_name,
+};
+
+static struct pic_softc armadaxp_err_pic = {
+ .pic_ops = &armadaxp_err_picops,
+ .pic_name = "armadaxp_err",
+};
+
static struct {
bus_size_t offset;
uint32_t bits;
@@ -180,6 +501,8 @@ static struct {
{ ARMADAXP_SDIO_BASE, (1 << 17) },
{ ARMADAXP_USB1_BASE, (1 << 19) },
{ ARMADAXP_USB2_BASE, (1 << 20) },
+ { ARMADAXP_CESA0_BASE, (1 << 23) },
+ { ARMADAXP_CESA1_BASE, (1 << 23) },
{ ARMADAXP_PEX2_BASE, (1 << 26) },
{ ARMADAXP_PEX3_BASE, (1 << 27) },
#if 0
@@ -207,7 +530,7 @@ armadaxp_intr_bootstrap(bus_addr_t pbase
panic("%s: Could not map MPIC percpu registers", __func__);
/* Disable all interrupts */
- for (i = 0; i < 116; i++)
+ for (i = 0; i < ARMADAXP_IRQ_SOURCES; i++)
MPIC_WRITE(ARMADAXP_MLMB_MPIC_ICE, i);
mvsoc_intr_init = armadaxp_intr_init;
@@ -217,16 +540,25 @@ static void
armadaxp_intr_init(void)
{
int ctrl;
+ void *ih __diagused;
/* Get max interrupts */
armadaxp_pic.pic_maxsources =
((MPIC_READ(ARMADAXP_MLMB_MPIC_CTRL) >> 2) & 0x7FF);
if (!armadaxp_pic.pic_maxsources)
- armadaxp_pic.pic_maxsources = 116;
+ armadaxp_pic.pic_maxsources = ARMADAXP_IRQ_SOURCES;
pic_add(&armadaxp_pic, 0);
+ /* Chain error interrupts controller */
+ MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_ERR_MASK, 0);
+ armadaxp_err_pic.pic_maxsources = ARMADAXP_IRQ_ERROR_SOURCES;
+ pic_add(&armadaxp_err_pic, ARMADAXP_IRQ_ERROR_BASE);
+ ih = intr_establish(ARMADAXP_IRQ_ERR_SUMMARY, IPL_HIGH, IST_LEVEL_HIGH,
+ pic_handle_intr, &armadaxp_err_pic);
+ KASSERT(ih != NULL);
+
ctrl = MPIC_READ(ARMADAXP_MLMB_MPIC_CTRL);
/* Enable IRQ prioritization */
ctrl |= (1 << 0);
@@ -291,6 +623,16 @@ armadaxp_pic_set_priority(struct pic_sof
MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_CTP, ctp);
}
+static void
+armadaxp_pic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len)
+{
+ if (irq > __arraycount(armadaxp_pic_source_names)) {
+ snprintf(buf, len, "Unknown IRQ %d", irq);
+ return;
+ }
+ strlcpy(buf, armadaxp_pic_source_names[irq], len);
+}
+
static int
armadaxp_find_pending_irqs(void)
{
@@ -323,6 +665,81 @@ armadaxp_pic_block_irq(struct pic_softc
MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_ISM, irq);
}
+static void
+armadaxp_err_pic_source_name(struct pic_softc *pic, int irq,
+ char *buf, size_t len)
+{
+ if (irq > __arraycount(armadaxp_err_pic_source_names)) {
+ snprintf(buf, len, "Unknown IRQ %d", irq);
+ return;
+ }
+ strlcpy(buf, armadaxp_err_pic_source_names[irq], len);
+}
+
+
+/*
+ * ARMADAXP_MLMB_MPIC_ERR_CAUSE
+ */
+static void
+armadaxp_err_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase,
+ uint32_t irq_mask)
+{
+ uint32_t reg;
+
+ KASSERT(irqbase == 0); /* XXX: support offset */
+
+ reg = MPIC_CPU_READ(ARMADAXP_MLMB_MPIC_ERR_MASK);
+ reg |= irq_mask;
+ MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_ERR_MASK, reg);
+}
+
+static void
+armadaxp_err_pic_block_irqs(struct pic_softc *pic, size_t irqbase,
+ uint32_t irq_mask)
+{
+ uint32_t reg;
+
+ KASSERT(irqbase == 0); /* XXX: support offset */
+
+ reg = MPIC_CPU_READ(ARMADAXP_MLMB_MPIC_ERR_MASK);
+ reg &= ~irq_mask;
+ MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_ERR_MASK, reg);
+}
+
+static void
+armadaxp_err_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
+{
+ uint32_t reg;
+
+ KASSERT(pic->pic_maxsources >= is->is_irq);
+
+ reg = MPIC_CPU_READ(ARMADAXP_MLMB_MPIC_ERR_MASK);
+ reg |= ARMADAXP_IRQ_ERROR_BIT(is->is_irq);
+ MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_ERR_MASK, reg);
+}
+
+static int
+armadaxp_err_pic_pending_irqs(struct pic_softc *pic)
+{
+ struct intrsource *is;
+ uint32_t reg;
+ int irq;
+
+ reg = MPIC_READ(ARMADAXP_MLMB_MPIC_ERR_CAUSE);
+ irq = ffs(reg);
+ if (irq == 0)
+ return 0;
+ irq--; /* bit number to index */
+
+ is = pic->pic_sources[irq];
+ if (is == NULL) {
+ printf("stray interrupt: %d\n", irq);
+ return 0;
+ }
+ return pic_mark_pending_sources(pic, 0, irq);
+}
+
+
/*
* Clock functions
*/
@@ -440,10 +857,10 @@ armadaxp_l2_init(bus_addr_t pbase)
reg = L2_READ(ARMADAXP_L2_AUX_CTRL);
reg &= ~(L2_AUX_WBWT_MODE_MASK);
reg &= ~(L2_AUX_REP_STRAT_MASK);
- reg |= L2_AUX_WBWT_MODE_WB;
reg |= L2_AUX_ECC_ENABLE;
reg |= L2_AUX_PARITY_ENABLE;
- reg |= L2_AUX_FORCE_WA;
+ reg |= L2_AUX_WBWT_MODE_BY_ATTR;
+ reg |= L2_AUX_FORCE_WA_BY_ATTR;
reg |= L2_AUX_REP_STRAT_SEMIPLRU;
L2_WRITE(ARMADAXP_L2_AUX_CTRL, reg);
@@ -659,3 +1076,64 @@ armadaxp_clkgating(struct marvell_attach
/* Clock Gating not support */
return 0;
}
+
+int
+armadaxp_init_mbus(void)
+{
+ struct mbus_table_def *def;
+ uint32_t reg;
+ int i;
+
+ for (i = 0; i < nwindow; i++) {
+ /* disable all windows */
+ reg = read_mlmbreg(MVSOC_MLMB_WCR(i));
+ reg &= ~MVSOC_MLMB_WCR_WINEN;
+ write_mlmbreg(MVSOC_MLMB_WCR(i), reg);
+ write_mlmbreg(MVSOC_MLMB_WBR(i), 0);
+ }
+
+ for (i = 0; i < __arraycount(mbus_table); i++) {
+ def = &mbus_table[i];
+ if (def->window >= nwindow)
+ continue;
+ if (def->size == 0)
+ continue;
+
+ /* restore window base */
+ reg = def->base & MVSOC_MLMB_WBR_BASE_MASK;
+ write_mlmbreg(MVSOC_MLMB_WBR(def->window), reg);
+
+ /* restore window configuration */
+ reg = MVSOC_MLMB_WCR_SIZE(def->size);
+ reg |= MVSOC_MLMB_WCR_TARGET(def->target);
+ reg |= MVSOC_MLMB_WCR_ATTR(def->attr);
+#ifdef AURORA_IO_CACHE_COHERENCY
+ reg |= MVSOC_MLMB_WCR_SYNC; /* enbale I/O coherency barrior */
+#endif
+ reg |= MVSOC_MLMB_WCR_WINEN;
+ write_mlmbreg(MVSOC_MLMB_WCR(def->window), reg);
+ }
+
+ return 0;
+}
+
+int
+armadaxp_attr_dump(struct mvsoc_softc *sc, uint32_t target, uint32_t attr)
+{
+ struct mbus_description *desc;
+ int i;
+
+ for (i = 0; i < __arraycount(mbus_desc); i++) {
+ desc = &mbus_desc[i];
+ if (desc->target != target)
+ continue;
+ if (desc->attr != attr)
+ continue;
+ aprint_verbose_dev(sc->sc_dev, "%s", desc->string);
+ return 0;
+ }
+
+ /* unknown decoding target/attribute pair */
+ aprint_verbose_dev(sc->sc_dev, "target 0x%x(attr 0x%x)", target, attr);
+ return -1;
+}
Index: src/sys/arch/arm/marvell/armadaxpreg.h
diff -u src/sys/arch/arm/marvell/armadaxpreg.h:1.4 src/sys/arch/arm/marvell/armadaxpreg.h:1.5
--- src/sys/arch/arm/marvell/armadaxpreg.h:1.4 Thu May 14 05:39:32 2015
+++ src/sys/arch/arm/marvell/armadaxpreg.h Wed Jun 3 02:53:19 2015
@@ -43,13 +43,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_UNITID_DDR MVSOC_UNITID_DDR
#define ARMADAXP_UNITID_DEVBUS MVSOC_UNITID_DEVBUS
-#define ARMADAXP_UNITID_MBUS MVSOC_UNITID_MBUS
#define ARMADAXP_UNITID_MLMB MVSOC_UNITID_MLMB
#define ARMADAXP_UNITID_PEX MVSOC_UNITID_PEX
#define ARMADAXP_UNITID_USB 0x5 /* USB registers */
#define ARMADAXP_UNITID_XORE0 0x6 /* Reserved? */
#define ARMADAXP_UNITID_GBE0 0x7
+#define ARMADAXP_UNITID_GBE1 0x7
#define ARMADAXP_UNITID_GBE2 0x3
+#define ARMADAXP_UNITID_GBE3 0x3
#define ARMADAXP_UNITID_PEX0 MVSOC_UNITID_PEX
#define ARMADAXP_UNITID_PEX1 0x8
#define ARMADAXP_UNITID_PEX2 MVSOC_UNITID_PEX
@@ -57,11 +58,47 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_UNITID_CRYPT 0x9
#define ARMADAXP_UNITID_SATA 0xa
#define ARMADAXP_UNITID_BM 0xc
-#define ARMADAXP_UNITID_PNC 0xc
+#define ARMADAXP_UNITID_NAND 0xd /* NAND registers */
#define ARMADAXP_UNITID_SDIO 0xd /* SDIO registers */
-#define ARMADAXP_UNITID_LCD 0xe /* Reserved? */
-#define ARMADAXP_UNITID_XORE1 0xf /* Reserved? */
+#define ARMADAXP_UNITID_LCD 0xe
+#define ARMADAXP_UNITID_XORE1 0xf
+/* DDR Attributes */
+#define ARMADAXP_ATTR_DDR_CS0 0x0e
+#define ARMADAXP_ATTR_DDR_CS1 0x0d
+#define ARMADAXP_ATTR_DDR_CS2 0x0b
+#define ARMADAXP_ATTR_DDR_CS3 0x07
+
+/* DEVBUS Attributes */
+#define ARMADAXP_ATTR_DEVBUS_UART 0x01
+#define ARMADAXP_ATTR_DEVBUS_SPI0_CS0 0x1e
+#define ARMADAXP_ATTR_DEVBUS_SPI0_CS1 0x5e
+#define ARMADAXP_ATTR_DEVBUS_SPI0_CS2 0x9e
+#define ARMADAXP_ATTR_DEVBUS_SPI0_CS3 0xde
+#define ARMADAXP_ATTR_DEVBUS_SPI0_CS4 0x1f
+#define ARMADAXP_ATTR_DEVBUS_SPI0_CS5 0x5f
+#define ARMADAXP_ATTR_DEVBUS_SPI0_CS6 0x9f
+#define ARMADAXP_ATTR_DEVBUS_SPI0_CS7 0xdf
+#define ARMADAXP_ATTR_DEVBUS_SPI1_CS0 0x1a
+#define ARMADAXP_ATTR_DEVBUS_SPI1_CS1 0x5a
+#define ARMADAXP_ATTR_DEVBUS_SPI1_CS2 0x9a
+#define ARMADAXP_ATTR_DEVBUS_SPI1_CS3 0xda
+#define ARMADAXP_ATTR_DEVBUS_SPI1_CS4 0x1b
+#define ARMADAXP_ATTR_DEVBUS_SPI1_CS5 0x5b
+#define ARMADAXP_ATTR_DEVBUS_SPI1_CS6 0x9b
+#define ARMADAXP_ATTR_DEVBUS_SPI1_CS7 0xdb
+#define ARMADAXP_ATTR_DEVBUS_DEV_CS0 0x3e
+#define ARMADAXP_ATTR_DEVBUS_DEV_CS1 0x3d
+#define ARMADAXP_ATTR_DEVBUS_DEV_CS2 0x3b
+#define ARMADAXP_ATTR_DEVBUS_DEV_CS3 0x37
+#define ARMADAXP_ATTR_DEVBUS_BOOT_CS 0x2f
+#define ARMADAXP_ATTR_DEVBUS_BOOT_ROM 0x1d
+
+/* NAND Attributes */
+#define ARMADAXP_ATTR_NAND_RESERVED 0x20
+
+/* PCIe Attributes */
+/* port 0, 1 has 4 lanes */
#define ARMADAXP_ATTR_PEXx0_MEM 0xe8
#define ARMADAXP_ATTR_PEXx0_IO 0xe0
#define ARMADAXP_ATTR_PEXx1_MEM 0xd8
@@ -70,11 +107,49 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_ATTR_PEXx2_IO 0xb0
#define ARMADAXP_ATTR_PEXx3_MEM 0x78
#define ARMADAXP_ATTR_PEXx3_IO 0x70
+/* port 2, 3 has only 1 lane */
#define ARMADAXP_ATTR_PEX2_MEM 0xf8
#define ARMADAXP_ATTR_PEX2_IO 0xf0
#define ARMADAXP_ATTR_PEX3_MEM 0xf8
#define ARMADAXP_ATTR_PEX3_IO 0xf0
+/* GbE Attributes */
+#define ARMADAXP_ATTR_GBE_RESERVED 0x00
+
+/* BM Attributes */
+#define ARMADAXP_ATTR_BM_RESERVED 0x00
+
+/* CRYPT Attributes */
+#define ARMADAXP_ATTR_CRYPT_SWAP_MASK __BITS(1,0)
+#define ARMADAXP_ATTR_CRYPT_SWAP_B (0x0 << 0)
+#define ARMADAXP_ATTR_CRYPT_SWAP_NONE (0x1 << 0)
+#define ARMADAXP_ATTR_CRYPT_SWAP_BW (0x2 << 0)
+#define ARMADAXP_ATTR_CRYPT_SWAP_W (0x3 << 0)
+#define ARMADAXP_ATTR_CRYPT_UNIT_MASK __BITS(3,2)
+#define ARMADAXP_ATTR_CRYPT_UNIT0 (0x1 << 2)
+#define ARMADAXP_ATTR_CRYPT_UNIT1 (0x2 << 2)
+
+#define ARMADAXP_ATTR_CRYPT0_NOSWAP \
+ (ARMADAXP_ATTR_CRYPT_SWAP_NONE|ARMADAXP_ATTR_CRYPT_UNIT0)
+#define ARMADAXP_ATTR_CRYPT0_SWAP_BYTE \
+ (ARMADAXP_ATTR_CRYPT_SWAP_B|ARMADAXP_ATTR_CRYPT_UNIT0)
+#define ARMADAXP_ATTR_CRYPT0_SWAP_BYTE_WORD \
+ (ARMADAXP_ATTR_CRYPT_SWAP_BW|ARMADAXP_ATTR_CRYPT_UNIT0)
+#define ARMADAXP_ATTR_CRYPT0_SWAP_WORD \
+ (ARMADAXP_ATTR_CRYPT_SWAP_W|ARMADAXP_ATTR_CRYPT_UNIT0)
+
+#define ARMADAXP_ATTR_CRYPT1_NOSWAP \
+ (ARMADAXP_ATTR_CRYPT_SWAP_NONE|ARMADAXP_ATTR_CRYPT_UNIT1)
+#define ARMADAXP_ATTR_CRYPT1_SWAP_BYTE \
+ (ARMADAXP_ATTR_CRYPT_SWAP_B|ARMADAXP_ATTR_CRYPT_UNIT1)
+#define ARMADAXP_ATTR_CRYPT1_SWAP_BYTE_WORD \
+ (ARMADAXP_ATTR_CRYPT_SWAP_BW|ARMADAXP_ATTR_CRYPT_UNIT1)
+#define ARMADAXP_ATTR_CRYPT1_SWAP_WORD \
+ (ARMADAXP_ATTR_CRYPT_SWAP_W|ARMADAXP_ATTR_CRYPT_UNIT1)
+
+
+#define ARMADAXP_IRQ_ERR_SUMMARY 4
+
#define ARMADAXP_IRQ_GBE0_TH_RXTX 8 /* GBE0_TH_RXTX_Int */
#define ARMADAXP_IRQ_GBE1_TH_RXTX 10 /* GBE1_TH_RXTX_Int */
#define ARMADAXP_IRQ_GBE2_TH_RXTX 12 /* GBE2_TH_RXTX_Int */
@@ -134,8 +209,37 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_IRQ_PEX2 99 /* PCIe Port2 INTA/B/C/D */
#define ARMADAXP_IRQ_PEX3 103 /* PCIe Port3 INTA/B/C/D */
+#define ARMADAXP_IRQ_SOURCES 116
-#define ARMADAXP_MLMB_NWINDOW 19
+/*
+ * IRQ mappings for Error Interrupt Cause(ARMADAXP_MLMB_MPIC_ERR_CAUSE)
+ */
+#define ARMADAXP_IRQ_ERROR_BASE 120
+#define ARMADAXP_IRQ_ERROR_SOURCES 32
+#define ARMADAXP_IRQ_ERROR(x) (120 + (x))
+#define ARMADAXP_IRQ_ERROR_BIT(irq) (1 << irq)
+
+#define ARMADAXP_IRQ_CESA0_ERR ARMADAXP_IRQ_ERROR(0)
+#define ARMADAXP_IRQ_DEVBUS_ERR ARMADAXP_IRQ_ERROR(1)
+#define ARMADAXP_IRQ_IDMA_ERR ARMADAXP_IRQ_ERROR(2)
+#define ARMADAXP_IRQ_XOR1_ERR ARMADAXP_IRQ_ERROR(3)
+#define ARMADAXP_IRQ_PEX0_ERR ARMADAXP_IRQ_ERROR(4)
+#define ARMADAXP_IRQ_PEX1_ERR ARMADAXP_IRQ_ERROR(5)
+#define ARMADAXP_IRQ_GBE_ERR ARMADAXP_IRQ_ERROR(6)
+#define ARMADAXP_IRQ_CESA1_ERR ARMADAXP_IRQ_ERROR(7)
+#define ARMADAXP_IRQ_USB_ERR ARMADAXP_IRQ_ERROR(8)
+#define ARMADAXP_IRQ_DRAM_ERR ARMADAXP_IRQ_ERROR(9)
+#define ARMADAXP_IRQ_XOR0_ERR ARMADAXP_IRQ_ERROR(10)
+#define ARMADAXP_IRQ_BM_ERR ARMADAXP_IRQ_ERROR(12)
+#define ARMADAXP_IRQ_CIB_ERR ARMADAXP_IRQ_ERROR(13)
+#define ARMADAXP_IRQ_PEX2_ERR ARMADAXP_IRQ_ERROR(15)
+#define ARMADAXP_IRQ_PEX3_ERR ARMADAXP_IRQ_ERROR(16)
+#define ARMADAXP_IRQ_SATA0_ERR ARMADAXP_IRQ_ERROR(17)
+#define ARMADAXP_IRQ_SATA1_ERR ARMADAXP_IRQ_ERROR(18)
+#define ARMADAXP_IRQ_TDM_ERR ARMADAXP_IRQ_ERROR(20)
+#define ARMADAXP_IRQ_NAND_ERR ARMADAXP_IRQ_ERROR(21)
+
+#define ARMADAXP_MLMB_NWINDOW 20
#define ARMADAXP_MLMB_NREMAP 8
/*
@@ -207,7 +311,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_MLMB_MPIC_IIACK 0xb4
#define ARMADAXP_MLMB_MPIC_ISM 0xb8
#define ARMADAXP_MLMB_MPIC_ICM 0xbc
-#define ARMADAXP_MLMB_MPIC_ERR_MASK 0xec0
+#define ARMADAXP_MLMB_MPIC_ERR_MASK 0xc0
/* Multiprocessor Interrupt Controller Shifts */
#define MPIC_CTP_SHIFT 28 /* Global priority level field */
@@ -252,15 +356,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define L2_CTRL_ENABLE (1 << 0)
/* ARMADAXP_L2_AUX_CTRL */
-#define L2_AUX_WBWT_MODE_MASK (3 << 0)
-#define L2_AUX_WBWT_MODE_BY_ATTR (0 << 0)
-#define L2_AUX_WBWT_MODE_WB (1 << 0)
-#define L2_AUX_WBWT_MODE_WT (2 << 0)
-#define L2_AUX_FLUSH_ON_POWERDOWN (1 << 3)
-#define L2_AUX_ECC_ENABLE (1 << 20)
-#define L2_AUX_PARITY_ENABLE (1 << 21)
-#define L2_AUX_INVAL_UCE (1 << 22)
-#define L2_AUX_FORCE_WA (1 << 23)
+#define L2_AUX_WBWT_MODE_MASK __BITS(1,0)
+#define L2_AUX_WBWT_MODE_BY_ATTR (0 << 0)
+#define L2_AUX_WBWT_MODE_WB (1 << 0)
+#define L2_AUX_WBWT_MODE_WT (2 << 0)
+#define L2_AUX_FLUSH_ON_POWERDOWN __BIT(3)
+#define L2_AUX_ECC_ENABLE __BIT(20)
+#define L2_AUX_PARITY_ENABLE __BIT(21)
+#define L2_AUX_INVAL_UCE __BIT(22)
+#define L2_AUX_FORCE_WA_MASK __BITS(24,23)
+#define L2_AUX_FORCE_WA_BY_ATTR (0 << 23)
+#define L2_AUX_FORCE_WA_DISABLE (1 << 23)
+#define L2_AUX_FORCE_WA_ENABLE (2 << 23)
+#define L2_AUX_FORCE_WA_ENABLE_DT (3 << 23)
#define L2_AUX_REP_STRAT_MASK (3 << 27)
#define L2_AUX_REP_STRAT_LFSR (1 << 27)
#define L2_AUX_REP_STRAT_PLRU (2 << 27)
@@ -325,6 +433,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_CESA0_BASE (UNITID2PHYS(CRYPT) + 0xd000) /* 0x9d000 */
#define ARMADAXP_CESA1_BASE (UNITID2PHYS(CRYPT) + 0xf000) /* 0x9f000 */
+#define ARMADAXP_XPSEC0_BASE (UNITID2PHYS(CRYPT) + 0x0000) /* 0x90000 */
+#define ARMADAXP_XPSEC1_BASE (UNITID2PHYS(CRYPT) + 0x2000) /* 0x92000 */
+
/*
* Serial-ATA Host Controller (SATAHC) Registers
*/
@@ -338,7 +449,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
/*
* NAND Flash Controller Version 2.0 Registers
*/
-#define ARMADAXP_NAND_BASE 0xc0000
+#define ARMADAXP_NAND_BASE (UINTID2PHYS(NAND))
/*
* PnC Unit Registers
Index: src/sys/arch/arm/marvell/armadaxpvar.h
diff -u src/sys/arch/arm/marvell/armadaxpvar.h:1.1 src/sys/arch/arm/marvell/armadaxpvar.h:1.2
--- src/sys/arch/arm/marvell/armadaxpvar.h:1.1 Wed Apr 15 10:40:36 2015
+++ src/sys/arch/arm/marvell/armadaxpvar.h Wed Jun 3 02:53:19 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxpvar.h,v 1.1 2015/04/15 10:40:36 hsuenaga Exp $ */
+/* $NetBSD: armadaxpvar.h,v 1.2 2015/06/03 02:53:19 hsuenaga Exp $ */
/*
* Copyright (c) 2015 SUENAGA Hiroki
* All rights reserved.
@@ -26,6 +26,7 @@
*/
#ifndef _ARMDAXPVAR_H_
#define _ARMDAXPVAR_H_
+#include <arm/marvell/mvsocvar.h>
#include <machine/bus_defs.h>
/* device initalization */
@@ -40,5 +41,8 @@ extern void armadaxp_sdcache_inv_range(v
extern void armadaxp_sdcache_wb_range(vaddr_t, paddr_t, psize_t);
extern void armadaxp_sdcache_wbinv_range(vaddr_t, paddr_t, psize_t);
-#endif /* _ARMDAXPVAR_H_ */
+/* mbus initialization */
+extern int armadaxp_init_mbus(void);
+extern int armadaxp_attr_dump(struct mvsoc_softc *, uint32_t, uint32_t);
+#endif /* _ARMDAXPVAR_H_ */
