CVS commit: src/sys/arch/arm/marvell

[SUENAGA Hiroki]

Module Name:    src
Committed By:   hsuenaga
Date:           Wed Apr 15 12:11:31 UTC 2015

Modified Files:
        src/sys/arch/arm/marvell: armadaxp.c

Log Message:
add L2 cache write eviction buffer sync barrier


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/marvell/armadaxp.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/arm/marvell/armadaxp.c
diff -u src/sys/arch/arm/marvell/armadaxp.c:1.9 src/sys/arch/arm/marvell/armadaxp.c:1.10
--- src/sys/arch/arm/marvell/armadaxp.c:1.9	Wed Apr 15 10:40:36 2015
+++ src/sys/arch/arm/marvell/armadaxp.c	Wed Apr 15 12:11:31 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: armadaxp.c,v 1.9 2015/04/15 10:40:36 hsuenaga Exp $	*/
+/*	$NetBSD: armadaxp.c,v 1.10 2015/04/15 12:11:31 hsuenaga Exp $	*/
 /*******************************************************************************
 Copyright (C) Marvell International Ltd. and its affiliates
 
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
 *******************************************************************************/
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.9 2015/04/15 10:40:36 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.10 2015/04/15 12:11:31 hsuenaga Exp $");
 
 #define _INTR_PRIVATE
 
@@ -485,6 +485,7 @@ void
 armadaxp_sdcache_wb_all(void)
 {
 	L2_WRITE(ARMADAXP_L2_WB_WAY, L2_ALL_WAYS);
+	L2_WRITE(ARMADAXP_L2_SYNC, 0);
 	__asm__ __volatile__("dsb");
 }
 
@@ -492,6 +493,7 @@ void
 armadaxp_sdcache_wbinv_all(void)
 {
 	L2_WRITE(ARMADAXP_L2_WBINV_WAY, L2_ALL_WAYS);
+	L2_WRITE(ARMADAXP_L2_SYNC, 0);
 	__asm__ __volatile__("dsb");
 }
 
@@ -515,6 +517,7 @@ armadaxp_sdcache_wb_range(vaddr_t va, pa
 	pa_end = (pa_base + sz) & ~0x1f;
 	L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
 	L2_WRITE(ARMADAXP_L2_WB_RANGE, pa_end);
+	L2_WRITE(ARMADAXP_L2_SYNC, 0);
 	__asm__ __volatile__("dsb");
 }
 
@@ -527,6 +530,7 @@ armadaxp_sdcache_wbinv_range(vaddr_t va,
 	pa_end = (pa_base + sz) & ~0x1f;
 	L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
 	L2_WRITE(ARMADAXP_L2_WBINV_RANGE, pa_end);
+	L2_WRITE(ARMADAXP_L2_SYNC, 0);
 	__asm__ __volatile__("dsb");
 }