Hello, On Thursday, April 01, 2010 1:17 PM jassi brar wrote:
> > There are some boards that do not strictly follow SPI standard and use > > only 3 wires (SCLK, MOSI or MISO, SS) for connecting some simple auxiliary > > chips and controls them with GPIO based 'spi controller'. In this > > configuration the MISO or MOSI line is missing (it is not required if the > > chip does not transfer any data back to host or host only reads data from > > chip). > > > > This patch adds support for such non-standard configuration in GPIO-based > > SPI controller. It has been tested in configuration without MISO pin. > Though not very clear atm, but wouldn't having some ineffective > virtual GPIO assigned > to this non-existing MISO/MOSI do the trick? This will be very hacky, also the platform would need to have some virtual GPIO only for this purpose. The proposed patch does it in the right way, especially because all required SPI master flags (SPI_MASTER_NO_TX and SPI_MASTER_NO_RX) are already merged to SPI core. Best regards -- Marek Szyprowski Samsung Poland R&D Center ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
