Hello, On Thursday, April 01, 2010 12:36 PM Marek Szyprowski wrote:
> There are some boards that do not strictly follow SPI standard and use > only 3 wires (SCLK, MOSI or MISO, SS) for connecting some simple auxiliary > chips and controls them with GPIO based 'spi controller'. In this > configuration the MISO or MOSI line is missing (it is not required if the > chip does not transfer any data back to host or host only reads data from > chip). > > This patch adds support for such non-standard configuration in GPIO-based > SPI controller. It has been tested in configuration without MISO pin. > > Reviewed-by: Kyungmin Park <[email protected]> > Signed-off-by: Marek Szyprowski <[email protected]> Is there any progress on merging this patch? It hangs on the patchwork for 2 months still marked as 'new'. I'm a bit confused. The idea behind the patch was already accepted (see commit 568d0697f42771425ae9f1e9a3db769fef7e10b6) but then the patch is still waiting... My fault I didn't asked for it on the beginning of the merge window. Best regards -- Marek Szyprowski Samsung Poland R&D Center ------------------------------------------------------------------------------ _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
