On Tue, Jun 1, 2010 at 5:48 AM, Marek Szyprowski <[email protected]> wrote: > Hello, > > On Thursday, April 01, 2010 12:36 PM Marek Szyprowski wrote: > >> There are some boards that do not strictly follow SPI standard and use >> only 3 wires (SCLK, MOSI or MISO, SS) for connecting some simple auxiliary >> chips and controls them with GPIO based 'spi controller'. In this >> configuration the MISO or MOSI line is missing (it is not required if the >> chip does not transfer any data back to host or host only reads data from >> chip). >> >> This patch adds support for such non-standard configuration in GPIO-based >> SPI controller. It has been tested in configuration without MISO pin. >> >> Reviewed-by: Kyungmin Park <[email protected]> >> Signed-off-by: Marek Szyprowski <[email protected]> > > Is there any progress on merging this patch? It hangs on the patchwork for > 2 months still marked as 'new'. I'm a bit confused. The idea behind the patch > was already accepted (see commit 568d0697f42771425ae9f1e9a3db769fef7e10b6) > but then the patch is still waiting... My fault I didn't asked for it on the > beginning of the merge window.
I'm not convinced this is the best approach. I did look at it, but decided not to merge it yet. It adds code to the hottest path in the spi-gpio driver (not that this driver will ever be fast, but on bit-banged gpio, every instruction counts). I was delayed it getting on the SPI backlog this merge cycle due to travel, so I've deferred making a decision on this patch. I'll be taking another look in the next few weeks and I'll let you know whether or not I'll pick it up for 2.6.36 g. ------------------------------------------------------------------------------ _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
