Poul-Henning Kamp wrote: > In message <[EMAIL PROTECTED]>, Bruce Griffiths writes: > >> Poul-Henning Kamp wrote: >> > > >> You still dont need a dedicated time count latch for each channel. >> A pair of time count latches should suffice (one for each >> counter/synchroniser clock transition polarity) plus a flag bit for each >> channel. >> Latch the flag bits and the count in both sets of latches. >> > > Nice theory, but if you try to compare say, to GPS receivers which > are very good, that doesn't work. > > Please explain why this doesnt work. You surely have stored exactly the same information just in a different format.
If you use 2 synchronisers, one clocked by the negative slope transition of the counter clock and the other by the positive slope transition of the counter clock, then the output of one synchroniser will be accurate /reliable, the problem is deciding which to use for any given sycnhroniser input transition. If one uses an interpolator then the correct synchroniser output can be determined (this has been done successfully), however this just offloads the problem to the interpolator. In any case with a well designed synchroniser the failure rate can be extremely low (Once in a billion years or longer with a PPS signal and a 100MHz clock). Bruce _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
