Poul-Henning Kamp wrote: > In message <[EMAIL PROTECTED]>, Bruce Griffiths writes: > > >> Explain why?? >> > > The signal you are trying to measure, for instance a 1PPS may > transistion right at the same time the FPGA clock does, that means > that the latch-bit may or may not make up it's mind about the > state, but usually, it will oscillate for some period. > > The standard prescription for this, is to feed the input signal > through a sequence of three latch-bits, clocked by the master clock, > in order to get it synchronized to the master clock. > > Once it's synchronized, you can use it to latch the counter value > without any trouble. > > Poul
As I suspected we had our wires crossed, I was talking about the counter value latches not the synchroniser latches /D-flipflops. Bruce _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
