OK, I am doing a 24-hour ADEV analysis of the HP 5328A Timebase Output when set to divide-by-10,000,000. I use the 10MHz output from an HP 8644A sig.gen. OCXO. I split that 10MHz signal into two; one end goes to the the input of the HP 5328A counter. The other 10MHz end goes to the Stop input of the 5370A. The Start input gets the 5328A Timebase Output PPS. The 5370A is free running. I have included the plot of what I get so far.
I would tend to say that the divider is pretty lousy for short term, but it is
all fine for longer runs, right?
Is this what I should expect from a TTL/ECL divider chain designed in the
'70s-'80s? How would this compare to a modern divider chain, like the PIC
divider or David Partridge's divider board?
Since I get a straight line pretty much up to 500s or so, do I conclude that
the divider dominates the system noise up to there?
Of course, the 5370A timebase drift has to be taken into account but is not
subtracted on that plot.
Thanks,
Bert.
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