John Miles wrote:
I would tend to say that the divider is pretty lousy for short
term, but it is all fine for longer runs, right?
Is this what I should expect from a TTL/ECL divider chain
designed in the '70s-'80s? How would this compare to a modern
divider chain, like the PIC divider or David Partridge's divider board?
The 5370 residual plot I mentioned in the other message was taken under
similar conditions as you describe, but with a TADD-2 divider, and is almost
100x better. IMHO the 5328A solution doesn't look like a good one, since
any inexpensive digital divider should be able to beat it.
It's true that factors like trigger levels and attenuator settings matter,
but this will be observed at the tens-of-picoseconds level in my experience,
not at 1ns+ timescales. Triggering on the correct edge is likely to be more
important. Try it both ways and see if you notice a difference.
OK, so I tried this myself. A sloppy setup but never the less... The
CNT-90 time-base output via a T-connection on B-channel and then over to
the A input of the HP 5328, selected START A and then the T.B. OUT over
to CNT-90 channel A. At 100 kHz setting on the HP 5328, the TI A->B
measurement on CNT-90 shows some jitter, but RMS jitter is below 400 ps
at least and ADEV readings somewhat below that.
A quick check for various settings doesn't show significantly
differences. The period-plot showed sine-like variations, so maybe some
50 Hz aliasing with the result.
Anyway, it doesn't look like Berts measurement. Then again, I did not do
PPS output.
Need to do some proper setup. This was on the level of running down the
lab for a quick testie. I knew that 5328 would come in handy as
reference one day. It just did.
Cheers,
Magnus
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