> I would tend to say that the divider is pretty lousy for short > term, but it is all fine for longer runs, right? > > Is this what I should expect from a TTL/ECL divider chain > designed in the '70s-'80s? How would this compare to a modern > divider chain, like the PIC divider or David Partridge's divider board?
The 5370 residual plot I mentioned in the other message was taken under similar conditions as you describe, but with a TADD-2 divider, and is almost 100x better. IMHO the 5328A solution doesn't look like a good one, since any inexpensive digital divider should be able to beat it. It's true that factors like trigger levels and attenuator settings matter, but this will be observed at the tens-of-picoseconds level in my experience, not at 1ns+ timescales. Triggering on the correct edge is likely to be more important. Try it both ways and see if you notice a difference. > Since I get a straight line pretty much up to 500s or so, do I > conclude that the divider dominates the system noise up to there? That's very safe to say (again, load that residual .tim file and display it next to your result and you'll understand instantly). > Of course, the 5370A timebase drift has to be taken into account > but is not subtracted on that plot. Slow drift in the 5370 timebase isn't an issue for two-channel ADEV measurements. If you had a problem involving excessive noise from either the timebase or trigger circuits at timescales close to your 1-second tau period, it could degrade the results, but that's extremely unlikely. -- john, KE5FX _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
