Inside an FPGA, CORDIC can be implemented performing quite fast. An
open-source implementation of CORDIC algorithm and a DDS using look-up
table or CORDIC can be found in OpenCores, gh_vhdl_lib.
Jim, thank you very much for all the excellent references, and
particularly the last one about the CORDIC variation. The Altera
simulations of its NCO showns significant more spurii for CORDIC
(traditional one) than the other alternatives for same phase accumulator
and magnitude precisions, and angular same angular resolution, but it is
by far the most effective in terms of FPGA usage.
Probably I will use the CORDIC approach in the implementation of my
digital down-converter, but the OpenCores core instead of the Altera IP,
if it is clean enough (the signal I need to downconvert is 8-bit
quantized and with poor S/N ratio, so some -40dB spurious will not have
significance).
Regards,
Javier
El 20/06/2011 21:17, [email protected] escribió:
Just a FYI, you don't have to use sine lookup tables. You can generate sine and
cosine on the fly with a coordic. Perhaps not easy at RF speed, but very common
in audio DSP.
-----Original Message-----
From: Jim Lux<[email protected]>
Sender: [email protected]
Date: Mon, 20 Jun 2011 12:04:24
To:<[email protected]>
Reply-To: Discussion of precise time and frequency measurement
<[email protected]>
Subject: Re: [time-nuts] DDS'ery
On 6/20/11 9:46 AM, Luis Cupido wrote:
Gracias, Javier.
As you read in my previous email I'm basically
worried about close-in spurs (those that
will pass through the PLL loop filter).
will digest that 4th section... tks.
...
Since I'm inside an FPGA... I'm eager to get
spurs down without leaving the digital world...
Anyone knows any literature covering that ?
Tons..
Jouko Vankka wrote whole books about it.
Direct Digital Synthesizers and transmitters for software radio
Direct Digital Synthesizers: Theory, Design and Applications
You might want to look at various Error Feedback/Error Filtering schemes
which allow you to use a smaller cosine table and/or smaller DAC and
have better spur performance.
Vankka, J, "A direct digital synthesizer with a tunable error feedback
structure", IEEE Trans on Comm, V45, #4, pp416-420, 1997
Vankka's EF technique works quite well at suppressing spurs close to the
carrier (at the expense of pushing them farther out).
Reinhardt, V, "Spur Reduction Techniques in Direct Digital
Synthesizers", Proc Intl Freq Control Symp, 1993
Flanagan, M., Zimmerman, G., "Spur-reduced digital sinusoid synthesis"
IEEE Trans on Comm, V43, #7, pp2254-2262, 1995
(this one is about using dither to spread the spurs out)
O'Leary, P., Maloberti, F., "A direct-digital synthesizer with improved
spectral performance", IEEE Trans on Comm, V39, #7, 1991
You might also look at some of the spur cancellation things, such as the
one implemented in some of AD's DDS parts.. Basically, it's a second NCO
that generates a coherent signal that is subtracted/added to the primary
signal to "notch" out the spur.
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Chief Technology Officer
HV Sistemas S.L. PHONE: +34 949 336 806
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