Yes that right. Is clear that I would have a 10ns jitter,
So the catch would be to find a scheme to spread spurs out or to push
them away from carrier. Then they would not bother me (would not pass
the PLL).
lc
ct1dmk.
On 6/21/2011 7:43 AM, Javier Herrero wrote:
But I forgot to add that the resultant jitter will be also the sampling
rate period (10ns at 100MHz), so I think that the output will not be too
clean... so I'm afraid it will not be a great improvement over using
only the MSB :)
Regards,
Javier
El 21/06/2011 08:37, Javier Herrero escribió:
I supppose that then you will need the digital version of the DDS ->
Filter -> Comparator think, usign a FIR and outputing the sign of the
resultant signal.
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