Dear Luis,
On 07/21/2011 05:30 PM, Luis Cupido wrote:
Magnus,
It crossed my mind of messing somehow with the phase
accumulator metrics but did not figure a way...
that is a good suggestion I will investigate in that direction...
(or maybe... if you do have a bit of free time to drop me
a couple of lines more, could you please detail
a bit more as so far I did not caught the idea clearly enough to start
coding...)
As I was tired I did not disclose enough details for implementation, but
selected to be brief to bring in the approach to see if it was "obvious"
or not.
OK.
A typical phase accumulator of n bits have N = 2^n possible states.
Considering that fout = fclk * M/N where M is the normal
phase-accumulator frequency control you can also realize that it takes
N/gcd(M,N) state-changes to come back to the original state, so it can
take a number of output cycles for all the beat frequencies to take
integer cycles.
If you instead want to select N freely you have to realize that while we
every clock cycle perform
P = P + M
we assume that the operation is modulus N, so the actual formula is
P = (P + M) mod N
but since N was of the form 2^n it is trivial to truncate the bit of and
just do N bit addition. So far I have only been very picky about details.
If we now want to choose N freely to be N <= 2^n we realize that we
still needs to do the modulus calculation.
Come to think of it, it always has two outcomes...
P = P + M
and
P = P + M - N
We can also know which to pick, since P cannot be larger than N and it
cannot be below zero, so assuming we have a P already within those
limits all it takes is a comparision of P
if (P+M >= N)
P = P + M - N
else
P = P + M
That is enough for simulation, but doesn't quite cut it for FPGA since
you would get the propagation delay of both the comparision and the
additions... on every cycle.
We can improve on this by calculating two potential sums, and watch the
carry from one of them to let a mux select between them. Also, the M-N
difference is fairly static, so we pre-calculate it.
precalc
O = M - N
cycle
P1 = P + M
C|P2 = P + O
if (C == 0)
P = P2
else
P = P1
That should give you all the M/N relationships you would like to play
with in a fairly sufficient FPGA structure. Much finer control over
spurioses that way. Still fairly cheap in FPGA terms.
I hope you have what you need to start fooling around. I could throw
together some VHDL code for you if you really need it. With above
re-definition of the problem the performance hit in fclk should not be
as severe as the naive approach.
Luis Cupido.
ct1dmk.
p.s. No problem with the delay... ;-)
As it ended with you not saying you had a good solution, I thought it
would be nice to send a message anyway.
Cheers,
Magnus
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