Clever! At least for your spectral measurements the signal never leaves the 
digital domain. What is the width of the multipliers involved in the mixing? 
Can you give me a clue, which ADCs you are working with in the front end?
> 
> ....In this application, DDS artifacts would ultimately show up as spurs
> on phase noise plots or as ripple in ADEV plots.....

This matches exactly my own observations in terms of ripple in the Tau-Sigma 
digram when i used a standard like DDS from AD for this purpose. Exactly this 
is why I got interested in the XILNX DDS compiler.  May be the ALTERA stuff is 
on the same level. Have used ALTERA FPGAs and CPLDs in the past but currently I 
am devoted to XILINX due to the easier availability in Germany.

Best regards
Ulrich Bangert, DF6JB

Am 21.06.2011 um 12:10 schrieb John Miles:

>>> to provide SFDR up to 150 dB (and I'd notice it if I were
>>> getting much less than that in practice.)
>> 
>> has pushed me up! When I tell the compiler to generate me a 150 dB SFDR
>> DDS
>> then it produces an block with 28 (!) bits output witdh for the DAC. So, I
>> am asking myself what wonder-chips you may be using as DAC for your DDS
>> that
>> features a dynamic range high enough to really measure a 150 dB SFDR?
> 
> It's being used as part of a digital downconverter in my case, not driving a
> DAC.  In this application, DDS artifacts would ultimately show up as spurs
> on phase noise plots or as ripple in ADEV plots.   I haven't seen any
> unaccounted-for spurs above -130 to -140 dBc (where they could be coming
> from pretty much anywhere), so I've been happy with the core's real-world
> performance. 
> 
> -- john, KE5FX
> 
> 
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Ulrich Bangert
Ortholzer Weg1
27243 Gross Ippener
Deutschland
Tel   +49 (0)4224 95071
Fax  +49 (0)4224 95072
Mob +49 (0)172 8006546
www.ulrich-bangert.de



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