Jim Lux wrote: > if you're talking asynchronous RS232 (the by far most common, these days) > off hand, I'd expect the jitter to be on the order of 1/8 bit time, uniformly > distributed. An awful lot of UART implementations generate a 8x clock to > sample the input and find the rising edge of > the start bit.
Funny you should mention that. I was just thinking about what the main contribution to RS232 jitter would be. For fpga purposes I've seen a lot of verilog/vhdl code that does precisely what you descibe. Use a clock that's 8 times the bit clock, which is useful for oversampling the RX. Funny that UART implementations do the exact same thing. regards, Fred _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
