On 10/23/11 11:39 AM, Poul-Henning Kamp wrote:
In message<[email protected]>, Jim Lux writes:
I'd have to go back to some pretty old
databooks, but I'll bet the x8 thing has been around since the 70s. Why
8, and not 4, is a better question...
The original standards text describes this in some detail, but I can't
remember which one of them it was (Not V.24, possibly V.28 ?)
Since the other end might be electromechanical, the system had to
be imune to a rate tolerance in the several %, as well as flank-jitter
and contact prell.
I think the electromechanicals top out at 110 bps, where you're running
a line synchronous motor (back to our discussion about line frequency
tolerance).. Aha.. another reason to obssess about line frequency..
that ASR33 teletype you've got in the backroom needs to be GPS
disciplined...
With 4x oversampling, your sampling point on the start bit
would be somewhere in the [37.5...62.5]% interval.
A 2.5% rate difference would eat 25% over 10 symbols, and you would
be left with +/-12.5% for jitter/prell.
8x oversampling gives you +/-18.75%, a full 50% better.
Yes.. I remember doing stackups of timing tolerance over some number of
characters, which is kind of funny now that I think about it, because
everything was crystal derived, and 1000ppm (0.1%) would be appallingly
bad. More a roundoff error from whatever crystal you used for your
system clock (like that 2 or 4 MHz for the Z80) and hoping that it
wasn't too far off. ( as opposed to going out and buying a 1.84... MHz
crystal and using another package to make a clock with it)
It was argued at the time, that the sampling point of the start bit
should be 75% into the start bit, because the prell is not symmetric,
but this was not adopted.
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