On 10/23/11 10:02 AM, Tijd Dingen wrote:
Jim Lux wrote:
if you're talking asynchronous RS232 (the by far most common, these days)
off hand, I'd expect the jitter to be on the order of 1/8 bit time, uniformly
distributed. An awful lot of UART implementations generate a 8x clock to
sample the input and find the rising edge of
the start bit.
Funny you should mention that. I was just thinking about what the main
contribution to RS232 jitter would be. For fpga purposes I've seen a lot of
verilog/vhdl code that does precisely what you descibe. Use a clock that's 8
times the bit clock, which is useful for oversampling the RX. Funny that UART
implementations do the exact same thing.
more that FPGA implementations copy time tested approaches used in
ASIC/MSI implementations. I'd have to go back to some pretty old
databooks, but I'll bet the x8 thing has been around since the 70s. Why
8, and not 4, is a better question... I think it's because of
propagation delays between the "edge detector" and the "sampler" (i.e.
it needs some number of clocks to determine that "yes we really did see
an edge" and set up the sampler in the correct divided down clock phase.
You want to sample in the middle of the bit time, which is 4 clocks
after the edge (actually, the first time would be 12 clocks after the
edge). A clock to latch the "detect", a clock or two to reset the
divide by 8 so it's in the right phase, etc.
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