Poul-Henning,

Do you need 16 bits or can you get by with a 12 bit ADC?

Have you considered using an FPGA for signal processing? It seems you need a 
fairly serious CPU to handle that much data.

Didier KO4BB

Sent from my BlackBerry Wireless thingy while I do other things...

-----Original Message-----
From: "Poul-Henning Kamp" <p...@phk.freebsd.dk>
Sender: time-nuts-boun...@febo.com
Date: Wed, 14 Mar 2012 22:16:38 
To: Discussion of precise time and frequency measurement<time-nuts@febo.com>
Reply-To: Discussion of precise time and frequency measurement
        <time-nuts@febo.com>
Subject: Re: [time-nuts] WWVB BPSK Receiver Project?

In message <4f6116ce.7080...@pacific.net>, Brooke Clarke writes:

>I sure would like a WWVB BPSK receiver for the new modulation. 

I've been playing with SDR and VLF signals for ages.  What you
want is an antenna, a 1MSPS ADC and a fast-ish CPU.

One very interesting thing you can do with that, is to make a
buffer 1000 samples long, and continously average the received
signal into it, round-robin format.

That amounts to a comb-filter for every n*1kHz signal, and a
trivial sin/cos multiplicator will give you the phase and
amplitude of every single radiotransmitter on n*1kHz up to
your antialias filter at the same time.

If you have CPU power, you can also receive Loran-C by making the
buffer GRI*10 (or *20, if you want the code) samples long.

I've long thought about building a board with one of the faster
ARM CPUs and a 1MSPS 16bit ADC for this, but nobody else seemed
interested, so I've just used my hacked up rig.

-- 
Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
p...@freebsd.org         | TCP/IP since RFC 956
FreeBSD committer       | BSD since 4.3-tahoe    
Never attribute to malice what can adequately be explained by incompetence.

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