I was not concerned about processing power on a PC (or Mac for that matter) but 
for the uC that was used in PHK's project.

Didier KO4BB


Sent from my BlackBerry Wireless thingy while I do other things...

-----Original Message-----
From: Chris Albertson <albertson.ch...@gmail.com>
Sender: time-nuts-boun...@febo.com
Date: Thu, 15 Mar 2012 15:48:41 
To: Discussion of precise time and frequency measurement<time-nuts@febo.com>
Reply-To: Discussion of precise time and frequency measurement
        <time-nuts@febo.com>
Subject: Re: [time-nuts] WWVB BPSK Receiver Project?

On Thu, Mar 15, 2012 at 3:13 PM, Poul-Henning Kamp <p...@phk.freebsd.dk> wrote:
> In message <20120315152620.8347488e049854218aed4...@kinali.ch>, Attila Kinali 
> w
> rites:
>
>>> Do you need 16 bits or can you get by with a 12 bit ADC?
>
> In general: The more the merrier, for a digital dude like me, having
> more bits is easier than getting AGC working correctly :-)
>
>>> Have you considered using an FPGA for signal processing? It seems
>> you need a fairly serious CPU to handle that much data.


"That much data" we are talking about 192K samples per second.   I can
routinely record multiple tracks of 192K audio and do processing in
real time and the CPU meter hardly moves  the bottom.    Even a
gigabit per second Ethernet port is not "a lot of data" on a modern
computer.

FPGAs and DSP come into play if you are talking about tens of millions
of samples per second with data rates above say 200Mb/Sec  But the
rate from an audio interface running 192K and 24-bits is still under
one megabyte per second.    An interesting ratio is the number of CPU
cycles available to process one sample.  On my Apple iMac that would
be about roughly  200,000 operations per data sample.

In real life SDR receivers even an older CPU can process the I and Q
channels and maintain a large graphic screen and send and receive data
over a network and still not be "maxed out"


Chris Albertson
Redondo Beach, California

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