Hi fellow time nuts, quite soon I'll have to come up with a clever idea to characterize a few chips of a 130nm BiCMOS technology for transients. Unfortunately, I'll have to look at something on the order of five dozen outputs per chip, all at the same time. If money and development time was no concern, I'd probably go with roughly 250 Multi-GSample ADCs and sample all the outputs simultaneously. Unfortunately, money is an issue (who would have guessed? ;-P ), and I can't put several years into making this all work. Not to speak of handling all the data generated...
The idea I have right now is employing something on the order of three to five comparators per output, fed with different trigger levels. That way I should be able to get some information on the transient shape as well. But then I'll have to throw a few hundred Time Interval Counters at the problem in order to get the information on the duration of the transients. So in general, amplitude information comes from the comparator trigger levels, time information from the TICs. What I expect from the DUTs is transients in the range between 1 and maybe 50 nanoseconds duration, but on some circuits they may be a lot quicker as the bipolars are wicked fast (about 3-5 ps gate delay in ECL inverters). What do you guys think, would a truckload of TICs do the job? Maybe not on the Bipolars, but at the plain CMOS this should do. Any hints? Best regards, Florian _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
