Hello, just few quick comments:
Unfortunately, I don't have a more precise technical spec. I'm just trying to find a viable solution to characterize a chip manufacturing process with regard to Single-Event Transients. As this is supposed to only be a side task for my PhD, I would prefer to use something that already exists. On the other hand, until now I have no own budget, so if I have to ask for money to buy stuff, it would better be something that can be used for oher purposes as well.
Agreed. Fortunately, TDCs are usually made to be flexible enough, unless they are tailored to a specific need of your application. What seemed to me at the beginning of your requests.
What I had in mind here was the tradeoff between the flexibility of an FPGA and the performance of a dedicated ASIC. Of course, this very much depends on which optimizations were done and which technology is targeted. (..)
In general, it's true. However, last year we have got results quite comparable to ACAM's ASIC within relatively slow FPGA. We need to perform more temperature-stability and aging tests to confirm the results.
Depends on what you refer to by "testing". I'll be definitely the wrong guy to ask for elaborated jitter measurements, especially in the single-digit picosecond range. But if testing means giving your stuff a shot to see if it fits my needs, I'm all in.
The second option. I will let you know after assembling our eval boards. They are 2-channel only.
Regards, Marek _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
