Hello,
On Sat, 8 Sep 2012, Florian Teply wrote:
(..) But then I'll have to throw a few hundred Time Interval Counters
at the problem in order to get the information on the duration of the
transients. So in general, amplitude information comes from the
comparator trigger levels, time information from the TICs.
What I expect from the DUTs is transients in the range between 1 and
maybe 50 nanoseconds duration, but on some circuits they may be a lot
quicker as the bipolars are wicked fast (about 3-5 ps gate delay in
ECL inverters).
What do you guys think, would a truckload of TICs do the job? Maybe not
on the Bipolars, but at the plain CMOS this should do.
It depends on how much precise you need the TICs (TDCs) to be. If it may
be around +-100ps..1ns, the solution is simple enough and some hundreds of
channels are feasible.
If you need units of ps, the challenge is big, IMHO. Currently, we are
testing our Time-to-Digit Converter within single FPGA, out last design
exhibited 7ps RMS of accuracy. In case you were interested, I expect
finishing of demo board during October. It would be more FPGA-resources
consuming, though.
Best regards,
Marek
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