Anders, I used an AD9858 years ago in our FireFox synthesizer product clocked at 1GHz locked to the on-board 10MHz GPSDO.
I used an ADF4002 or 4000 (can't remember) pll with integer division driving a UMC (now Sirenza) VCO. It worked very well and there where no 10MHz spurs measurable. Its very easy to get rid of reference feedthrough by using a good low pass filter on the EFC input and proper layout technique. I used a 5KHz bandwidth or so. The Analog Devices PLL simulator tool makes it a breeze to design the loop filter and predict output performance. Choosing a VCO with limited modulation BW also helps keep the reference away from the output. You can even select VCOs from a list of programmed parts in the AD software. Today I would not use a simple (cheap) 1GHz VCO anymore because of the relatively high phase noise, and some if them require up to 20V drive voltage. I would use a Crystal based product such as our ULN-1G 1GHz crystal oscillator. That part may be overkill since it has DC-DC regulators, filters, mil-temp range, and a +22dBm temp-stabilized output amplifier, but its a drop-in replacement for a VCO. With that part, the loop filter bandwidth can be reduced to a couple 100Hz to take advantage of the very low PN of the oscillator. If price is an issue, and you just need a one-off then you can build your own 1GHz crystal VCXO: Use a third harmonic crystal to run a single transistor oscillator at 125MHz (or buy a 125MHz low-noise oscillator). A third harmonic crystal will allow a wider frequency control range than a fifth harmonic, which may be needed to compensate aging and temp effects on the crystal.Then multiply by four using a simple RC resonant circuit in a common emitter driver. Follow this by another driver to get +10dBm or so. Then use a diode doubler (Mini Circuits etc) to get 1GHz output, and buffer that output with an RF transistor, or an LVDS driver chip etc. you may want to follow that with a mini circuits 1200MHz low pass filter to get rid of any residual 1500MHz f3 spurs. But depending on your needs a passive, five or six component LP filter driven by an ADF400x and a standard 1GHz VCO may just do the trick. You should be able to get an ADF400x eval board cheaply and swap out the VCO to a 1GHz unit from Ebay and program the board using a PC or micro-controller. Caveat Emptor: I tried other PLL vendors, and they were not as good as Analog. Also stay away from fractional-n PLLs for phase noise and spurs. Voila. Bye, Said Sent From iPhone On Dec 30, 2013, at 9:56, Anders Wallin <[email protected]> wrote: > I've tested the AD9912 evaluation board: > http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png > > I want to use it with a 10MHz external input clock, but it looks like the > on-board PLL that generates a 1200MHz sample clock from my input isn't that > great, since I get strong side-bands on the output that are only 18-20 dB > down from the fundamental. > > So it looks like I need to supply a clean 800-1000MHz clock to the DDS to > get a clean output. Any ideas/suggestions for generating this from a 10 MHz > sine? > Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A) > would be possible but I'd prefer a PLL from 10MHz if it's doable > simply/cheaply. > > Anders > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
