Am 30.12.2013 16:56, schrieb Anders Wallin:
I've tested the AD9912 evaluation board:
http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png
I want to use it with a 10MHz external input clock, but it looks like the
on-board PLL that generates a 1200MHz sample clock from my input isn't that
great, since I get strong side-bands on the output that are only 18-20 dB
down from the fundamental.
So it looks like I need to supply a clean 800-1000MHz clock to the DDS to
get a clean output. Any ideas/suggestions for generating this from a 10 MHz
sine?
Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A)
would be possible but I'd prefer a PLL from 10MHz if it's doable
simply/cheaply.
I'm planning to do something similar as a ADC sample clock.
(and an offset generator)
Over Xmas, I got as far as locking a MTI-260 to my house reference,
giving clean 10 MHz + distrib amp .
Next step will be locking a 100 MHz VCXO to the 10 MHz, it's less ado
than multiplying and filtering. This will be a Pascall in the long run or
sth. homebrew. For now, I'll try a Crystek CVHD-950. Close-in noise
will be governed by the MTI-260 anyway.
2 doublers with absolutely minimum filtering on 200 MHz and then
2 SAW-Filters on 400 MHz against 100, 200, 300, 500, 600, 700... MHz
<
http://www.digikey.de/product-search/de?pv7=2&k=495-3923-1-nd&mnonly=0&newproducts=0&ColumnSort=0&page=1&quantity=0&ptm=0&fid=0&pageSize=25
>
< http://media.digikey.com/pdf/Data%20Sheets/Epcos%20PDFs/B3742.pdf >
They are €1,90 @ 1.
Finally, a doubler or tripler to 800 or 1200 MHz. Sub/harmonics are now
far away
and easily removed.
The SAW filters would also do most of the filtering work when I multiplied
directly *2 *5 from 10 to 100 MHz.
Finally, a few days to build sth. interesting!!! :-)
regards, Gerhard
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