Hej Anders,
On 31/12/13 08:31, Anders Wallin wrote:
Thanks for all replies so far!
It looks like I will play around with the evaluation board some more, and
see if I can get the on-chip PLL to behave better.
The settings with 2x edge-detector and 60x PLL were the only ones I could
find where the output frequency setting in the software corresponded to the
actual output frequency - hence I tested only with 10MHz x120 = 1200 MHz
sysclock. I have asked about this on the AD forum, but no replies yet.
If that doesn't work the suggested ADF4351 (or similar) evaluation board
looks like the most straightforward option.
Looking at the datasheet, it looks like you are pushing it a bit hard
from the reference clock side of things. Using double-edge trigger is a
good way to upset things, as rising and falling edge, as detected, may
cause re-occuring stress in either direction, so it's not ideal.
Sniffing the loop at pin 31 would give you a hint if it is pumping every
50 ns or so.
I would consider of using a 100 MHz OCXO as an intermediate step. Lock
it to your 10 MHz in a high-bandwidth PI loop and then feed it to the
AD9912 board.
What is your tool of choice for checking the phase-noise?
Cheers,
Magnus
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