Anders
I've used the AD9912 Eval board with great success - spurs with the
on-chip clock multiplier were >-60dBc, IIRC, maybe better.
My guess is that you are pushing the on-chip VCO too high - do you
really need a 1200MHz system clock? The AD9912 is only specified for a
sys. clock of 1000MHz, and the on-chip VCO is also only specified to
1000MHz - yes, I know that the Eval software allows other values, but
the VCO actually has quite a narrow frequency range (10%) in order to
improve phase noise, and uses switchable on-chip inductors to select the
correct output frequency range, the highest being 900-1000MHz. I'd be
surprised if it locks at 1200MHz.
First thing is to try a 1000MHz clock.
regards
Grant Hodgson
From: Anders Wallin <anders.e.e.wal...@gmail.com>
To: Discussion of precise time and frequency measurement
<time-nuts@febo.com>
Subject: [time-nuts] sysclock source for AD9912 DDS?
I've tested the AD9912 evaluation board:
http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png
I want to use it with a 10MHz external input clock, but it looks like the
on-board PLL that generates a 1200MHz sample clock from my input isn't that
great, since I get strong side-bands on the output that are only 18-20 dB
down from the fundamental.
So it looks like I need to supply a clean 800-1000MHz clock to the DDS to
get a clean output. Any ideas/suggestions for generating this from a 10 MHz
sine?
Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A)
would be possible but I'd prefer a PLL from 10MHz if it's doable
simply/cheaply.
Anders
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