Hello, I want to design a digital phase lock loop.
I intend to lock a 10 MHz ultra low noise oscillator that we make to an external frequency standard. I need a digital PLL as I’m trying to get a loop bandwidth < 0.1 Hz. Has anyone had any experience of Digital PLL’s or can point me to any documents published? Regards Steve _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
