Hoi Attila
Yes, the only way to reduce emitter-emitter inductance is indeed to connect
them on the die. Its even better if the current source transistor collector is
also connected to the common emitter node of the long tailed pair on the die as
this minimises the capacitance at this node.
Alternatively one can add a small series resistance to reduce the associated
emitter circuit time constant as Wavecrest do.
The Wavecrest patent is somewhat detailed and complete with reasonably detailed
circuit diagrams and explanatory text.
US6185509
US6194925 ***************
US6226231US4908784
Bruce
On Tuesday, 10 May 2016 9:17 PM, Attila Kinali <[email protected]> wrote:
Hoi Bruce,
On Mon, 9 May 2016 23:34:24 +0000 (UTC)
Bruce Griffiths <[email protected]> wrote:
> Its probably easier/cheaper to construct a suitable filter for a GSPS ADC
> than to construct a TAC that is fast enough to suit an ADC with a GHz clock.
Probably.
> Minimising the emitter to emitter inductance of a longtailed pair or
> equivalent is key to achieving a fast enough switching time for a suitable
> TAC.
How does one minimize this inductance? The only way I am aware of is
to use a package with a pair of transistors with common emiter pin.
> The somewhat heroic measures employed in the Wavecrest counters is
> perhaps the limit of discrete construction techniques.
Are these heroic measures documented somewhere?
So far I have not even seen a block diagram of a Wavecrest counter,
much less a schematic.
Attila kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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