Yes, just a synchroniser clocked with the same clock as the ADC.The
interpolator measures the synchroniser delay by charging the capacitor in the
interval between the occurrence of the transition to be time stamped and when
the output of the synchroniser recognises this transition.The ADC samples the
capacitor voltage on the next clock.In reality the ADC samples its input
continuously and the relevant sample is flagged by the synchroniser and
associated logic.
Buffering the capacitor voltage avoids the need to correct for the effect of
sampling the capacitor voltage during runup.However the buffer isn't essential
as long as the correction is made and the ADC input is essentially
capacitive.The ramp capacitor should be somewhat larger than the ADC input
capacitance.
Bruce
On Monday, 9 May 2016 12:01 PM, Gerhard Hoffmann <[email protected]> wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
....
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
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