Hi,
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
Cheers,
Magnus
On 05/04/2016 10:46 AM, Bruce Griffiths wrote:
Integrating A Time interval to charge TAC at the front end of a capacitive
charge redistribution SAR ADC should allow a conversion time of 300ns or so..
Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate
without too many cascaded gates in the selection logic for the next available
TAC.
Bruce
On Wednesday, 4 May 2016 12:00 PM, Bruce Griffiths
<[email protected]> wrote:
On Tuesday, May 03, 2016 02:31:17 PM Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
Massive parallelism of a simple NUTT style interpolator (charge capacitor with
say 10mA, rundown with say 1uA, use 100MHz clock or faster clock ).
With a custom IC for the analog part, a resolution of 1ps should be feasible.
An FPGA can do all the non critical stuff like the rundown counting.
The problem is to ensure that the front end logic that selects the next non-
busy interpolator doesn't accumulate excessive jitter from cascaded gates.
The same issue of accumulated jitter produced by cascaded gates/inverters can
limit the performance of vernier delay line style interpolators. Minimising
the number of series inverters by using a higher frequency clock (100MHZ,
1GHz??) should help somewhat.
Bruce
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