On Mon, June 13, 2016 6:51 pm, Bob Camp wrote: > ... The ECL inputs to an FPGA rarely do have lower noise.
I was confused about that at first, the original poster was using external ECL receivers for sampling, but had CMOS outputs to transmit the data to the FPGA. That sounds to me like a one bit quantizer, which has approximately 6dB dynamic range (neglecting for the moment things such as non-linearity and aliasing). I don't see how you get any decent resolution of where the edge transition actually occurs. -- Chris Caudle _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
