If the quantisation noise is random and spread uniformly over the Nyquist
bandwidth (~40MHz??) then the noise floor is about -82dBc/Hz.If a pair of
independent quantisers is employed then by using cross correlation techniques
it should be possible to lower the system noise floor to -100dBC/Hz or less.
The problem lies in ensuring that the quantisation noise is actually
random..With a high resolution RF ADC internal noise is usually sufficient (>=
1 lsb)) to ensure this.
Bruce
On Tuesday, 14 June 2016 2:11 PM, Bruce Griffiths
<[email protected]> wrote:
The subsequent all digital mixdown and low pass filtering, if done correctly,
will increase the resolution provided that the signal and reference periods are
uniformly sampled at a sufficient equivalent number of points. But with a
starting point some 70dB or more behind an ADC, the system noise floor wont be
particularly low.
Bruce
On Tuesday, 14 June 2016 1:28 PM, Chris Caudle <[email protected]>
wrote:
On Mon, June 13, 2016 6:51 pm, Bob Camp wrote:
> ... The ECL inputs to an FPGA rarely do have lower noise.
I was confused about that at first, the original poster was using external
ECL receivers for sampling, but had CMOS outputs to transmit the data to
the FPGA.
That sounds to me like a one bit quantizer, which has approximately 6dB
dynamic range (neglecting for the moment things such as non-linearity and
aliasing). I don't see how you get any decent resolution of where the
edge transition actually occurs.
--
Chris Caudle
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