The idea here is around a 80MHz sample clock with a maximum input/ref
signal of around 25MHz. This is based on the TimePod with ADCs, which is
supposed to work with square waves. Its is using a 77MHz clock if I
remember correctly, so somewhere in the neighborhood of 12-13 ns per sample.
When you feed a square wave into this you have several samples at say
50, then it jumps to 50,000 stays there for several samples, then jumps
down to 50 again. This still seems like a binary sample. The difference
is that every now and then the sample hits during a ramptime of the
square wave and will give some intermediate value, is this enough of a
difference to invalidate the concept of a binary sample?
Or is the difference that the ADC won't stay at 50, but will be bouncing
around say between 45 and 55 when the square wave is low and this noise
makes it work? If that is the case then wouldn't a longer measurement
time do essentially the same thing with slight variations of timing of
the edge due to the noise in the binary sampler?
John S.
On 6/13/2016 8:17 PM, Chris Caudle wrote:
On Mon, June 13, 2016 9:38 pm, Bruce Griffiths wrote:
If the quantisation noise is random and spread uniformly over the Nyquist
bandwidth (~40MHz??) then the noise floor is about -82dBc/Hz.
How do you spread the quantization noise randomly with a one bit
quantizer? I'm mostly familiar with single bit quanitizers in the context
of audio range delta-sigma converters where the quantizer is in a feedback
loop to move most of the noise to a higher frequency range. That also
requires a clock much higher than the minimum nyquist requirement.
Maybe I need to see a block diagram of what is being described. Where is
the clock for the ECL flip-flop generated? I don't recall seeing a
description of what the effective sample rate will be, or the highest
clock signal accepted for analysis.
With a high resolution RF ADC internal noise is usually sufficient
(>= 1 lsb)) to ensure this.
Can't really dither to >= 1lsb when lsb=msb (single bit quantizer).
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