On Thursday, September 22, 2016 01:37:02 AM Gerhard Hoffmann wrote:
> Am 22.09.2016 um 00:24 schrieb Bruce Griffiths:
> > Another issue is the requirement to trim the current sink for low 
output
> > offset.
> 
> And _that_ FET is made from Unobtainium.
> 
> > If one takes advantage of the fact that the PLL imposes a low
> > frequency cutoff to the PN measurements, the amplifier input   can be 
AC
> > coupled, allowing dc bias feedback to be applied to the input device 
gate.
> > Use a parallel dc coupled JFET input opamp for the PLL
> 
> That's what I did. Original Burr-Brown opa2134, time to use them up..
> 
> > Paralleled BF862's can be substituted for the input JFET.
> 
> Yep!
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One still has to deal with the negative R in series with negative C input 
impedance component which will cause peaking with source resistance 
greater than a few ohms (typically 1k source resistance shows significant 
gain peaking at high frequencies near the upper end of the amplifiers 
bandwidth).

Bruce
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