Am 22.09.2016 um 00:24 schrieb Bruce Griffiths:
For the later, Bruce commented that an jFET input stage would
probably be more quiet. Gerhard Hoffman has designed a similar
I must insist in my second "n" Hoffmann :-)
system that uses a couple of paralel low noise opamps instead
of a jfet stage and claims a noise floor of 220pV/sqrt(Hz). All of
these would need to be adapted to imporve thier frequency response
up to 10MHz (or actually a bit higher), but then the input stage
gets also a bit simpler as you don't need the huge capacitors anymore.
The ADA4898 has ft= 50 MHz, so that will be hard. It already takes some
to get to 2 MHz with the new FET amp.
Another issue is the requirement to trim the current sink for low output
offset. If one takes advantage of the fact that the PLL imposes a low
frequency cutoff to the PN measurements, the amplifier input can be AC
coupled, allowing dc bias feedback to be applied to the input device gate.
Use a parallel dc coupled JFET input opamp for the PLL
Using a single ended input stage is significantly quieter than using a
Paralleled BF862's can be substituted for the input JFET.
Hi, Bruce and Attila (and ...),
the JFET version of my preamp is making progress. It supports either upto 16
BF862 or 2 pairs of Interfet IF3602. Upper bandwidth limit will be 2 MHz if
it runs like the simulation. There is also a low gain DC output for the PLL.
One is populated with BF862, the other with Interfet. The 3rd will be
according to the outcome of the first tests, so that I have 2 equal ones for
X correlation. There will be some leftover boards available, but not to
into the drawer.
Soldered them last weekend, debug them on the next :-)
I expect 170 pV/rt Hz at least for the Interfet version. That is
probably pearls before
swine after a ring mixer, but then we are nuts.
Attila, you are just half an hour of driving away, at least during the
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