On 4/15/2018 2:17 PM, Magnus Danielson wrote:

On 04/14/2018 06:45 PM, John Larkin wrote:
Hi, Magnus,

We did a little PC board that has two Analog Devices CML comparators
that feed the flop.


An external DAC tweaks the VBIAS voltage to slew the edge times across
one another, and an external ADC looks at the averaged flop outputs. The
jitter noise floor is probably dominated by the test signals, not the
flop under test.
Ah, thanks. Much clearer now!

You more tweak the voltage than actual timing, it's the slope property
that does the timing, but interesting never the less.

Downstream of the comparators, all the flop sees is time... not voltage shift. We used a sampling scope to calibrate the picoseconds-per-volt slope of the voltage input from the DAC.

********************************** arb

John Larkin, President
Highland Technology, Inc
18 Otis Street
San Francisco, CA 94103

phone 415 551-1700   fax 551-5129

This is a Highland Technology confidential communication

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Reply via email to