Current PICDIV concept generates exactly 50% output duty cycles, so only even dividing factors are possible. If we accept a slightly unbalanced duty cycles (ex: one more instruction on the down side loop than for the up side loop), one could generalize to odd factors. (An idea suggested by Didier Juges) What would be the down sides for a Clock signal ? Gilles.
> Le 18 juin 2020 à 13:58, Gilles Clement <[email protected]> a écrit : > > Hi > I need to divide the output of an OCXO by a factor D=81 for testing purposes. > So with minimum added phase noise. > PICDIV-like approches would not work (D needs to be divisible by 8 or at > least be even) > I went through the archives and it seems that an Injection Locked Frequency > Divider with resynchronization flip-flop could be a simple and acceptable > solution. > As described in the following Wenzel paper: Unusual Frequency > Dividerswww.wenzel.com › uploads › dividers > <https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwik49qGpIvqAhURahQKHTBVClAQFjABegQIARAB&url=http%3A%2F%2Fwww.wenzel.com%2Fwp-content%2Fuploads%2Fdividers.pdf&usg=AOvVaw2m-9lURROiSbG9XykiDNDU> > Does this make sense? > Gilles. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
