Hi

Ok, that’s all very do-able with “normal” CMOS logic and standard counter
configurations. There is no need for anything exotic. Two divide by 9’s or 
4 divide by threes would do the trick. Anything derived from the 74161
will give you a quick low chip count answer. Bert’s XOR divider will give
you symmetric output. 

Any family from 74ls on should be fast enough. 

Bob

> On Jun 21, 2020, at 3:30 AM, Gilles Clement <[email protected]> wrote:
> 
> Hi,
> Comparing a reference signal at 162kHz with local 10MHz ocxo. Expected Adev 
> 10E-11 at 10sec.
> 162kHz / 81 = 2kHz = 10MHz / 5000
> GC
> 
>> Le 21 juin 2020 à 05:49, Bob kb8tq <[email protected]> a écrit :
>> 
>> Hi
>> 
>> *Any* divide approach followed by a flip flop clocked by the input clock 
>> will meet
>> that same basic requirement. While it *sounds* like it would improve things, 
>> it 
>> very much depends on the details.
>> 
>> What are you trying to do? What is the input frequency? What is the phase 
>> noise 
>> requirement?
>> 
>> Bob
>> 
>>> On Jun 20, 2020, at 2:22 PM, Gilles Clement <[email protected]> wrote:
>>> 
>>> Hi Robert,
>>> You are right, its the lambda divider that was discussed. Need to better 
>>> understand this approach....
>>> 74HC40103 could also do the 81 Pi-divide easily,  but I tend to prefer the 
>>> PICDIV concept where the controller is clocked by the signal to divide (So 
>>> limited or no noise is  added). AVR family could do it, as most of the 
>>> instructions take only one clock.
>>> Gilles.
>>> 
>>> 
>>>>> Le 20 juin 2020 à 19:48, Robert LaJeunesse <[email protected]> a écrit :
>>>> 
>>>> Gilles, if I read the Calosso-Rubiola paper correctly a Pi divider is 
>>>> pretty much your standard square-wave producing digital divider, such as a 
>>>> 74163 (for even divides). There's odd-value (3,5,7) Pi dividers shown at 
>>>> https://www.theremin.us/Circuit_Library/symmetrical_digital_dividers.html. 
>>>> What the Calosso-Rubiola paper promotes is the Lambda divider, which is 
>>>> depicted in figure 2 of the paper.
>>>> 
>>>> Bob L. 
>>>> 
>>>>> Sent: Friday, June 19, 2020 at 10:27 AM
>>>>> From: "Gilles Clement" <[email protected]>
>>>>> To: "Poul-Henning Kamp" <[email protected]>
>>>>> Cc: "Discussion of precise time and frequency measurement" 
>>>>> <[email protected]>
>>>>> Subject: Re: [time-nuts] Frequency division by 81
>>>>> 
>>>>> Hi, 
>>>>> Could you point me to a practical design example of a Pi divider ?
>>>>> 
>>>>> 
>>>>> Envoyé de mon iPad
>>>>> 
>>>>>>> Le 19 juin 2020 à 08:56, Poul-Henning Kamp <[email protected]> a 
>>>>>>> écrit :
>>>>>> 
>>>>>> --------
>>>>>> 
>>>>>>> I need to divide the output of an OCXO by a factor D=81 for testing 
>>>>>>> purposes. So with minimum added phase noise.
>>>>>> 
>>>>>> Two stages of divide by 9 PI-dividers ?
>>>>>> 
>>>>>> http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf
>>>>>> 
>>>>>> -- 
>>>>>> Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
>>>>>> [email protected]         | TCP/IP since RFC 956
>>>>>> FreeBSD committer       | BSD since 4.3-tahoe    
>>>>>> Never attribute to malice what can adequately be explained by 
>>>>>> incompetence.
>>>>> 
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