Hi,
On 2024-08-11 01:59, noneofyourbusiness wrote:
8cbbd2b88ac39815c79918610313984cc58db2bf
I propose supporting several syntaxes, at most only those that the RISC-V
specifications themselves showcase.
RV32I V2.1:
jalr x0, ra, 0
"C" extension V2.0:
jalr x0, 0(rs1)
RISC-V ABI V1.0:
jalr ra, ra, 0
jalr t1, t3
currently
jalr x0, 0(rs1)
jalr x0, ra, 0
won't work
P.S. vector examples add more injury to the optional arg problem:
vle32.v v0, (a1)
vle32.v v0, (a1), v0.t
I've been working on supporting the RISC-V specification syntax, and you
can see how I did it on many instructions. When I started working on
this tinycc used this syntax for loads and stores:
```
ld rd, rs, offset
```
It even had the input registers inverted in the store instruction. I
converted it to:
```
ld rd, offset(rs)
```
As it should be.
I didn't do it with every instruction. I made enough to make Musl build,
but I didn't have the time to continue doing this. I even implemented
several pseudo instructions where the arguments have default values, but
all the structure of the assembler is designed for the old (and
non-standard) syntax. It needs more work.
The relocation system is also in the way, and we need to reorganize a
little. Currently it adds a relocation when it reads a symbol, but
that's not what it should do, as RISC-V has many different cases for
relocations.
In summary, RISC-V assembler needs more work, I tried to make it more
similar to the standard, but only made the effort in basic instructions,
not in vector and compressed cases.
Best,
Ekaitz
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