On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: > This configures the PLL5P clock frequency to something in the ballpark of > 1GHz and allows more choices for MBUS and G2D clock frequency selection > (using their own divisors). In particular, it enables the use of 2/3 clock > speed ratio between MBUS and DRAM. > > Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Ian Campbell <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
