Le ven. 13 mars 2026 à 16:20, David Lechner <[email protected]> a écrit : > > On 3/13/26 9:49 AM, Julien Stephan wrote: > > Le mar. 10 mars 2026 à 16:34, David Lechner <[email protected]> a écrit > > : > >> > >> Replace the hard-coded xtal rate for PLL parents with struct mtk_parent. > >> > >> This avoids declaring the same clock rate in multiple places and will > >> allow future drivers to use an arbitrary clock. > >> > >> The variable is renamed to something that better indicate what the field > >> is actually used for. > >> > > ... > > >> +enum { > >> + CLK_PAD_CLK26M, > >> +}; > >> + > > > > Can we define these enum values in a common header? > > For example, CLK_PAD_CLK26M is defined in various different soc > > specific drivers. > > I would rather not, they depend on which external clocks are available > on a specific MCU. So they will rarely be the same. As you will see > in the later patches, more are added and they aren't always the same. > And the values need to be sequential for the lookup array, so we can't > have one enum that works for all SoCs. > > > Also clk-mt8189.c uses defines instead of enum, so maybe we should > > stay consistent. > > Hmm... I did that one first before I established the pattern. The values > are arbitrary, which is why I went with the enum here. I can clean that > up when I apply the patches. >
Fair enough. In that case, for the whole series Reviewed-by: Julien Stephan <[email protected]> > > > >> +static const ulong ext_clock_rates[] = { > >> + [CLK_PAD_CLK26M] = 26 * MHZ, > >> +}; > >> +
