Hi Pavel, On 5/17/2026 9:24 PM, Pavel Golikov wrote: > RK3566 has the same DDR memory controller as RK3568 has. The only > difference is a maximum supported DDR frequency. > > Limit maximum DDR frequency in DDR loader params, so DDR controller can > be initialized on both RK3566 and RK3568 SoCs.
This should likely be moved to a Kconfig option unless we can detect SoC variant at runtime. I know we can do it using OTP, but maybe there is some other hw reg we can readl() to figure out rk3566 vs rk3568? Regards, Jonas > > Signed-off-by: Pavel Golikov <[email protected]> > --- > drivers/ram/rockchip/sdram-rk3568-loader_params.inc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/ram/rockchip/sdram-rk3568-loader_params.inc > b/drivers/ram/rockchip/sdram-rk3568-loader_params.inc > index d9beea3519a..3fcc70d8495 100644 > --- a/drivers/ram/rockchip/sdram-rk3568-loader_params.inc > +++ b/drivers/ram/rockchip/sdram-rk3568-loader_params.inc > @@ -17,7 +17,7 @@ > 0, 0, /* reserved */ > > /* ddr4 */ > -(1560 << DDR_FREQ_F0_SHIFT) | (324 << DDR_FREQ_F1_SHIFT), > +(1056 << DDR_FREQ_F0_SHIFT) | (324 << DDR_FREQ_F1_SHIFT), > (528 << DDR_FREQ_F2_SHIFT) | (780 << DDR_FREQ_F3_SHIFT), > (0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), > /* drv when odt on */ > @@ -39,7 +39,7 @@ > (0x1 << PHY_CLK_SR_SHIFT), > > /* lpddr4 */ > -(1560 << DDR_FREQ_F0_SHIFT) | (324 << DDR_FREQ_F1_SHIFT), > +(1056 << DDR_FREQ_F0_SHIFT) | (324 << DDR_FREQ_F1_SHIFT), > (528 << DDR_FREQ_F2_SHIFT) | (780 << DDR_FREQ_F3_SHIFT), > (0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), > >
