Current fractional PLL code for RK3588 (also applies to RK3576) has two issues causing it to overshoot the requested frequency for some negative values of the fractional coefficient: one due to rounding, the other due to treating -32768 as an invalid value where it is actually valid. It also overflows the calculation of the fractional PLL rate when reading it back, causing the function to return wrong PLL frequencies for non- trivial values of the fractional coefficient.
Fix all three, and also use native signed integer arithmetics to avoid manual bitwise operations on the unsigned representation of the fractional coefficient, which simplifies the code and makes it easier to read. The commits are deliberately split into excruciating granularity to ensure each step is explained and easy to review. The final diff is not too large though, so I'd be happy to squash as required. Signed-off-by: Alexey Charkov <[email protected]> --- Alexey Charkov (6): clk: rockchip: pll: drop misleading fout in rockchip_rk3588_pll_k_get() clk: rockchip: pll: fix rounding of negative k in RK3588 frac PLL clk: rockchip: pll: fix RK3588 frac PLL result for k=-32768 clk: rockchip: pll: let rockchip_rk3588_pll_k_get update m directly clk: rockchip: pll: fractional PLL coefficient is two's complement clk: rockchip: pll: fix overflow and drop manual two's complement in rk3588_pll_get_rate arch/arm/include/asm/arch-rockchip/clock.h | 2 +- drivers/clk/rockchip/clk_pll.c | 70 ++++++++++++------------------ 2 files changed, 29 insertions(+), 43 deletions(-) --- base-commit: 6741b0dfb41dc82a284ab1cff4c58af6ef2f3f9c change-id: 20260713-rk3588-fracpll-7b3e1f817c7d Best regards, -- Alexey Charkov <[email protected]>
